IA186XL/IA188XL
16-Bit Microcontrollers
Data Sheet
July 6, 2011
4.
Functional Description
The follow descriptions apply to both the IA186XL and IA188XL unless otherwise noted.
Module descriptions are followed by descriptions of special operating modes.
Additional information on the operation and programming of the 80C186XL/80C188XL can be
found in the following Intel® publications:
80C186XL/80C188XL and 80L186XL/80L188XL 16-Bit High-Integration Embedded
Processors (272433-006)
80C186XL/80C188XL Microprocessor User’s Manual (270830-00n)
4.1
Device Architecture
Architecturally, the IA186XL microcontrollers include the following functional modules:
Bus Interface Unit
Clock Generator
Interrupt Control Unit
Timer/Counter Unit
Chip-Select Unit
Refresh Control Unit
Power-Save Control
DMA Unit
A functional block diagram of the IA186XL/IA188XL is shown in Figure 10. Descriptions of
the functional modules are provided in the follow subsections.
Control registers for the peripheral modules are located in a 256 byte control block. This block
can be mapped to either memory or I/O space. The offset map for addressing these registers is
given in Table 12.
4.1.1 Bus Interface Unit
A local bus controller generates the local bus control signals. It also employs a hold/hlda
protocol for relinquishing the local bus to other bus masters. Its outputs can be used to enable
external buffers and to direct the flow of data on and off the local bus. The bus controller is
responsible for generating 20 bits of address, read and write strobes, bus-cycle status information
and data. This controller is also responsible for reading data from the local bus during a read
operation. Synchronous and asynchronous ready input pins are provided to extend a bus cycle
beyond the minimum four clocks. The bus controller also generates two control signals (den_n
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