IA64250
Histogram/Hough Transform Processor
Data Sheet
August 19, 2008
LUT RAM Hough Transform Mode
(45 <
90):
Address
0
1
.
.
.
.
511
Memory Contents
0*cot
1*cot
.
.
.
.
511*cot
LUT RAM Find Pixel Mode:
Address
0
1
.
.
.
.
511
Memory Contents
0-5
Flag for Grey Value
0
Flag for Grey Value
1
.
.
.
.
Flag for Grey Value
511
6-7
t0
t1
Tag
Bit
t511
8
Not Used
Computation Mode
Histogram Computation:
During histogram computation, the ACC RAM and LUT RAM form the active elements of
the data path. The ACC RAM is addressed by the controller block. The ACC RAM address
is the DI input signal. The data addressed by the DI signal is incremented if the DV input
signal is high, otherwise the data is left unchanged. The LUT is not used in the computation
of the histogram and can concurrently modify the image by a user-defined transfer function.
The DI signal addresses the LUT and the LUT data appears on the VDO output pins two
clock cycles later.
Histogram equalization can be performed in real time. The histogram is stored in the ACC
RAM. The equalization transfer function must be computed and transferred into the LUT
RAM. Then during the next frame as a new histogram is being computed, data will also be
equalized in real time and passed to the VDO output pins.
IA211011114-01
Page 13 of 24
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