IA64250
Histogram/Hough Transform Processor
Data Sheet
August 19, 2008
WRITE LUT
The writing of data into the LUT RAM is similar to the operations described above, except
that the data to write into the RAM is placed on the CI bus when STARTIOn is low.
However, as described above, the processor will not return to the pixel processing mode
until IODV returns low.
The net result of this is that the IA64250 enters the I/O mode as soon as the STARTIOn
pin is pulled low and does not return to the pixel processing mode until IODV returns low.
The I/O mode will last N + 3 CLK2 cycles, where N is the number of RAM elements
written.
Writing LUT RAM
CLK2
STARTIO
CI[7:0]
IODV
Short I/O Cycle
RAM0
RAM1
RAM2
XXXX
XXXX
XXXX
XXXX
Start of Long I/O Cycle:
CLK2
STARTIO
CI
IODV
RAM0
RAM1
RAM2
RAM3
RAM4
RAM5
RAM6
End of Long I/O Cycle:
CLK2
STARTIO
CI
IODV
RAM508
RAM509
RAM510
RAM511
XXX
XXXX
XXXX
IA211011114-01
Page 18 of 24
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