IA6805E2
Microprocessor Unit
As of Production Version 00
29 August 2007
I/O Pin Functions
R/W-n DDR
I/O Pin Functions
0
0
The I/O pin is in input mode. Data is
written into the output data latch.
0
1
Data is written into the output data latch and
output to the I/O pin.
1
0
The state of the I/O pin is read.
1
1
the I/O pin is in an output mode. The
output data latch is read.
I/O Port Circuitry and Register Configuration:
DATA DIRECTION
REGISTER
BIT
TO
AND
FROM
LATCHED
OUTPUT
DATA BIT
OUTPUT
I/O
PIN
CPU
INPUT
REG
BIT
INPUT
I/O
PIN
7
6
5
4
3
2
1
0
$0004 ($0005)
DATA DIRECTION
DDA7 DDA6 DDA5 DDA4 DDA3 DDA2 DDA1 DDA0
A(B)
(DDB7) (DDB6) (DDB5) (DDB4) (DDB3) (DDB2) (DDB1) (DDB0)
REGISTER
PORT A(B)
REGISTER
$0000 ($0001)
PIN
PA7
(PB7)
PA6
(PB6)
PA5
(PB5)
PA4
(PB4)
PA3
(PB3)
PA2
(PB2)
PA1
(PB1)
PA0
(PB0)
Figure 2. PA0-PA7/PB0-PB7 (Input/Output Lines)
Copyright
©
2007
©
IA211081401-03
www.Innovasic.com
Customer Support:
1-888-824-4184
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