IA82050
Asynchronous Serial Controller
Data Sheet
February 25, 2011
IA82510
A(2:0)
D(7:0)
RDn
WRn
CSn
INT
RESET
RECEIVER
RXD
CTSn
RTSn
TIMING
(Baud Rate
Generators A & B,
Clocking
PIN
CONFIGURATION
DSRn or TA or OUT0n
DCDn or ICLK or OUT1n
DTRn or TB
MODEM
BUS INTERFACE
(Reset Logic,
Registers,
Interrupt Generation,
TRANSMITTER
TXD
CONFIG., STATUS, RXDATA
TXDATA
X1 or CLK
X2 or OUT2n
SCLK or RIn
Figure 2. Functional Block Diagram
®
IA211030617-08
UNCONTROLLED WHEN PRINTED OR COPIED
Page 8 of 22
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