IA82510
ASYNCHRONOUS SERIAL CONTROLLER
AC Characteristics
Parameter
CLK period
CLK period
CLK Low Time
CLK High Time
Min
54 ns
54 ns
25 ns
25 ns
250 ns
108 ns
Max
Data Sheet
As of Production Ver. 01
Notes
Divide by Two
No Divide by
10 ns
CLK Rise Time
10 ns
CLK Fall Time
CLK Rise Time
CLK Fall Time
Crystal Frequency
Reset Width
RTS/DTR Low Setup
to Reset inactive
RTS/DTR Low Hold
after Reset inactive
RDn Active Width
Address/CSn Setup
Time to RDn Active
Address/CSn Hold
after RDn Inactive
RDn or WRn Inactive
to Active Delay
Data Out Float Delay
after RDn Inactive
WRn Active Width
Address CSn Setup
Time to WRn Active
Address and CSn
hold Time after WRn
Data in Setup Time
to WRn Inactive
Data In Hold Time
after WRn Inactive
SCLK Period
SCLK Period
RXD Setup Time to
SCLK High
RXD Hold Time after
SCLK High
TXD Valid after SCLK
Low
TXD Delay after RXD
1 Mhz
8 * Clock Period
6 * Clock Period
15 ns
15 ns
20 Mhz
Divide by Two
Measured between 0.3 * VDD
and 0.7 * VDD
Divide by Two
Measured between 0.3 * VDD
and 0.7 * VDD
No Divide by
No Divide by
Clock Period – 20 ns
2* clock period +
65 ns
7 ns
0 ns
Clock Period +
15 ns
40 ns
2 * Clock Period
+ 15 ns
7 ns
0 ns
90 ns
12 ns
216 ns
3500 ns
250 ns
250 ns
170 ns
170 ns
Remote Loopback
16x Clocking Mode
1x Clocking Mode
Copyright
©
2001
ENG211001219-01
The End of Obsolescence™
innovASIC
www.innovasic.com
Customer Support:
1-888-824-4184
Page 7 of 14
INNOVASIC [ INNOVASIC, INC ]
