IA8044/IA8344
SDLC Communications Controller
Data Sheet
March 30, 2010
5.
AC Specifications
AC characteristics, external data memory characteristics, serial interface characteristics, and
external clock drive characteristics are provided in Tables 48 through 51, respectively.
TA
=
−
40 C to +85 C, VDD = 5V
10%, VSS = 0V, Load Capacitance = 87pF
Table 48. External Program Memory Characteristics
12 MHz Osc
Min
Max
171
–
75
–
74
–
–
298
83
–
254
–
–
215
0
–
–
76
91
–
–
373
-9
–
996
–
Variable Clock
1/TCLCL = 3.5 MHz to 12 MHz
Min
Max
2TCLCL+4
–
TCLCL-8
–
TCLCL-9
–
–
4TCLCL-35
TCLCL
–
3TCLCL+4
–
–
3TCLCL-35
0
–
–
TCLCL-7
TCLCL+8
–
–
5TCLCL-43
-9
–
12TCLCL
–
Symbol
TLHLL
TAVLL
TLLAX
TLLIV
TLLPL
TPLPH
TPLIV
TPXIX
TPXIZ
TPXAV
TAVIV
TAZPL
TCY
Parameter
ALE Pulse Width
Address Valid to ALE Low
Address Hold After ALE Low
ALE Low to Valid Instr. In.
ALE Low to PSENn Low
PSENn Pulse Width
PSENn Low to Valid Instr. In
Input Instr. Hold After PSENn
Input Instr. Float After PSENn
PSENn to Address Valid
Address to Valid Instr. In
Address Float to PSENn
Machine cycle
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Table 49. External Data Memory Characteristics
12 MHz Osc
Min
Max
487
–
487
–
74
–
–
383
0
–
–
165
–
633
–
708
250
250
325
–
76
–
563
–
86
–
Variable Clock
1/TCLCL = 3.5 MHz to 12 MHz
Min
Max
6TCLCL-13
–
6TCLCL-13
–
TCLCL-9
–
–
5TCLCL-35
0
–
–
2TCLCL-2
–
8TCLCL-34
–
9TCLCL-42
3TCLCL
3TCLCL
4TCLCL-8
–
TCLCL-7
–
7TCLCL-20
–
TCLCL+3
–
Symbol
TRLRH
TWLWH
TLLAX
TRLDV
TRHDX
TRHDZ
TLLDV
TAVDV
TLLWL
TAVWL
TQVWX
TQVWH
TWHQX
Parameter
RDn Pulse Width
WRn Pulse Width
Address Hold After ALE
RDn Low to Valid Data In
Data Hold After RDn
Data Float After RDn
ALE Low to Valid Data In
Address to Valid Data In
ALE Low to RDn or WRn Low
Address to RDn or WRn Low
Data Valid to WRn Transition
Data Setup Before WRn High
Data Held After WRn
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
®
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