IL145567
(V
CC
= 5V
±
5%, V
BB
= -5V
±
5%, values of all signals are indicated relatively to GNDA)
Characteristics
Frequencies of main clock oscillators
MCLK
X
or
MCLK
R
Symbol
fm
min
–
–
1.544
2.048
Min width of high or low pulse
Min width of high or low pulse
MCLK
X
or
MCLK
R
BCLK
X
or
BCLK
R
FS
X
or FS
R
t
w(M)
t
w(B)
t
w(FL)
t
r
t
f
f
B
t
su(BRM)
t
su(MFB)
t
h(BF)
t
su(FB)
t
d(BD)
t
d(BTS)
t
d(ZC)
t
d(ZF)
t
su(DB)
t
h(BD)
t
su(F)
t
h(F)
t
h(BFI)
100
50
50
50
50
128
50
20
20
80
20
20
50
20
0
50
50
50
–
50
–
ns
ns
ns
ns
ns
kHz
ns
ns
ns
ns
140
140
140
140
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
typical
max
Unit
Dynamic characteristics of digital signals
Min width of low pulse
Rise time
Fall time
Ratings of data bit synchronisation BCLK
X
or BCLK
R
Presetting time of from low BCLK
X
to high MCLK
R
Presetting time from high MCLK
X
to low BCLK
X
Holding time from low BCLK
X
(BCLK
R
) to high FS
X
(FS
R
)
Presetting time from high FS
X
(FS
R
) to low BCLK
X
(BCLK
R
) for
long frames
Delay time from high BCLK
X
to setting correct data on D
X
Delay time from high BCLK
X
to low
TS
X
Delay time of inhibition of output data D
X
relatively to 8
th
clock
pulse BCLK
X
Time of setting correct data after entry of signals FS
X
or BCLK
X
( the later of them)
Time of presetting data D
R
relatively to clock pulse BCLK
R edge
Holding time from low BCLK
R
to switching off D
R
Presetting time from high level FS
X
(FS
R
) to low level BCLK
X
(BCLK
R
) under synchronisation standard Short Frame
Holding time from low level BCLK
X
(BCLK
R
) to low level FS
X
(FS
R
) for synchronisation Short Frame
Holding time from 2
nd
period of low level BCLK
X
(BCLK
R
) to low
level FS
X
(FS
R
) for synchronisation Long Frame
4096
–
4
INTEGRAL [ INTEGRAL CORP. ]
