IN5851
pin is connected to the common part in general applications.
Oscillator
RC1-RC3
7,8,9
The IN5851N contains on-chip inverters to provide oscillator which will operate
with a minimum external components.
Following figure shows the on-chip configuration with the necessary external
components. Optimum stability occurs with the ration K=RS/R equal to 10
The oscillator period is given by:
T=RC(1.386+(3.5KCS)/C-(2K/(K+1)) in (K/(1.5K + 0.5))
Where CS is the stray capacitance on Pin 7.
Accuracy and stability will be enhanced with this capacitance minimized.
PPS
M/B
10
11
10/20pps Select
Connecting this pin to GND (pin 6) will select an output pulse rate of 10pps.
Connecting the pin VCC (pin 1) will select an output pulse rate of 20pps.
Make/break Select
The Make/Break pin controls the Make/Break ratio of the pulse output. The
make/Break ratio is controlled by connection VCC or GND to this pin as shown in
the following table.
Input
VCC (Pin1)
GND(PIn 6)
Make
33.4%
40%
Break
66.6%
60%
____
Mute
12
17
Mute Output
The mute output is an open-drain N-Channel transistor designed to drive external
bipolar transistor.
This circuitry is usually used to mute the receiver during outpulsing. As shown in
Fig. 2 the IN5851N mute output turns on (pulls to the VGND-supply) at the
beginning of the predigital pause and turns off (goes to an open circuit) following
the last break.
The delay from the end of the last break until the mute output turns off is mute
overlap and is specified as tMO
ON-HOOK/TEST
.
OH
This pin detects the state of the hook switch contact “OFF HOOK” corresponds to
VSS condition. ÖN HOOK”corresponds to VDD condition. When outpulsing in this
mode, which can be up to 300msec, is completed, the circuit is deactivated and
will require current only necessary to sustain the memory and power-up-clear
detect circuitry (refer to the electrical specifications).
3
INTEGRAL [ INTEGRAL CORP. ]
