TECHNICAL DATA
IN74AC112
Dual J-K Flip-Flop
with Set and Reset
High-Speed Silicon-Gate CMOS
The IN74AC112 is identical in pinout to the LS/ALS112,
HC/HCT112. The device inputs are compatible with standard CMOS
outputs; with pullup resistors, they are compatible with LS/ALS
outputs.
Each flip-flop is negative-edge clocked and has active-low
asynchronous Set and Reset inputs.
•
Outputs Directly Interface to CMOS, NMOS, and TTL
•
Operating Voltage Range: 2.0 to 6.0 V
•
Low Input Current: 1.0
µA;
0.1
µA
@ 25°C
•
High Noise Immunity Characteristic of CMOS Devices
•
Outputs Source/Sink 24 mA
ORDERING INFORMATION
IN74AC112N Plastic
IN74AC112D SOIC
T
A
= -40° to 85° C for all
packages
PIN ASSIGNMENT
LOGIC DIAGRAM
FUNCTION TABLE
Inputs
Set
L
H
L
H
H
H
H
H
H
H
PIN 16=V
CC
PIN 8 = GND
Reset
H
L
L
H
H
H
H
H
H
H
L
H
Clock
X
X
X
J
X
X
X
L
L
H
H
X
X
X
K
X
X
X
L
H
L
H
X
X
X
Outputs
Q
H
L
L
*
L
H
Q
L
H
L
*
H
L
No Change
Toggle
No Change
No Change
No Change
* Both outputs will remain low as long as Set and Reset are
low, but the output states are unpredictable if Set and Reset
go high simultaneously
X = Don’t Care
127