欢迎访问ic37.com |
会员登录 免费注册
发布采购

IN74AC112D 参数 Datasheet PDF下载

IN74AC112D图片预览
型号: IN74AC112D
PDF下载: 下载PDF文件 查看货源
内容描述: 双JK触发器具有​​置位和复位高速硅栅CMOS [Dual J-K Flip-Flop with Set and Reset High-Speed Silicon-Gate CMOS]
分类和应用: 触发器
文件页数/大小: 5 页 / 179 K
品牌: INTEGRAL [ INTEGRAL CORP. ]
 浏览型号IN74AC112D的Datasheet PDF文件第2页浏览型号IN74AC112D的Datasheet PDF文件第3页浏览型号IN74AC112D的Datasheet PDF文件第4页浏览型号IN74AC112D的Datasheet PDF文件第5页  
TECHNICAL DATA
IN74AC112
Dual J-K Flip-Flop
with Set and Reset
High-Speed Silicon-Gate CMOS
The IN74AC112 is identical in pinout to the LS/ALS112,
HC/HCT112. The device inputs are compatible with standard CMOS
outputs; with pullup resistors, they are compatible with LS/ALS
outputs.
Each flip-flop is negative-edge clocked and has active-low
asynchronous Set and Reset inputs.
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2.0 to 6.0 V
Low Input Current: 1.0
µA;
0.1
µA
@ 25°C
High Noise Immunity Characteristic of CMOS Devices
Outputs Source/Sink 24 mA
ORDERING INFORMATION
IN74AC112N Plastic
IN74AC112D SOIC
T
A
= -40° to 85° C for all
packages
PIN ASSIGNMENT
LOGIC DIAGRAM
FUNCTION TABLE
Inputs
Set
L
H
L
H
H
H
H
H
H
H
PIN 16=V
CC
PIN 8 = GND
Reset
H
L
L
H
H
H
H
H
H
H
L
H
Clock
X
X
X
J
X
X
X
L
L
H
H
X
X
X
K
X
X
X
L
H
L
H
X
X
X
Outputs
Q
H
L
L
*
L
H
Q
L
H
L
*
H
L
No Change
Toggle
No Change
No Change
No Change
* Both outputs will remain low as long as Set and Reset are
low, but the output states are unpredictable if Set and Reset
go high simultaneously
X = Don’t Care
127