TECHNICAL DATA
IN74AC373
Octal 3-State Noninverting
Transparent Latch
High-Speed Silicon-Gate CMOS
The IN74AC373 is identical in pinout to the LS/ALS373,
HC/HCT373. The device inputs are compatible with standard CMOS
outputs; with pullup resistors, they are compatible with LS/ALS
outputs.
These latches appear transparent to data (i.e., the outputs change
asynchronously) when Latch Enable is high. When Latch Enable goes
low, data meeting the setup and hold time becomes latched.
The Output Enable input does not affect the state of the latches, but
when Output Enable is high, all device outputs are forced to the high-
impedance state. Thus, data may be latched even when the outputs are
not enabled.
•
Outputs Directly Interface to CMOS, NMOS, and TTL
•
Operating Voltage Range: 2.0 to 6.0 V
•
Low Input Current: 1.0
µA;
0.1
µA
@ 25°C
•
High Noise Immunity Characteristic of CMOS Devices
•
Outputs Source/Sink 24 mA
ORDERING INFORMATION
IN74AC373N Plastic
IN74AC373DW SOIC
T
A
= -40° to 85° C for all
packages
PIN ASSIGNMENT
LOGIC DIAGRAM
FUNCTION TABLE
Inputs
Output
Enable
L
L
PIN 20=V
CC
PIN 10 = GND
L
H
Latch
Enable
H
H
L
X
D
H
L
X
X
Output
Q
H
L
No Change
Z
X = Don’t Care
Z = High Impedance
416
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