IZ0065
PIN DESCRIPTION
PIN
№
INP/
OUTP
NAME
Operating Voltage
Negative Supply
Voltage
Bias Voltage
DESCRIPTION
For logical circuit (+5 V
±
10%, +3 V
±
10%)
0 V (GND)
For LCD driver circuit (-5 V)
INTER-
FACE
Power
Supply
V
DD
(24)
GND (34)
Power
V
EE
(31)
Input
Bias voltage level for LCD drive (select level)
V
1
V
2
(44,45)
LCD driver
LCD driver output
SC
1
÷
SC
20
Output
Input
PART 1
Bias Voltage
Bias voltage level for LCD drive (nonselect level)
V
3
V
4
(46,47)
Input
Data interface Selection of the shift direction of Part 1 shift register
SHL1
(41)
SHL1
DL1
DR1
V
DD
out
in
V
SS
in
out
DL1,DR1
Input/
(35,36)
Output
SC
21
÷
SC
40
V
5
V
6
(48,49)
SHL2
(42)
Output
Input
Input
PART 2
LCD driver
Bias Voltage
Data input/output of Part 1 shift register
Power
LCD
Power
V
DD
or
V
SS
Controller
or
IZ0065
LCD driver output
Bias voltage level for LCD drive (nonselect level)
Power
V
DD
or
V
SS
Data interface Selection of the shift direction of Part 2 shift register
SHL2
DL2
DR2
V
DD
out
in
V
SS
in
out
Data input/output of Part 2 shift register
DL2,DR2
Input/
(37,38)
Output
M
(40)
Input
Alternated
signal for LCD
driver output
Data shift / latch clock
Mode selection
Controller
or
IZ0065
Controller
PART
1
2
FCS
V
SS
V
DD
V
SS
V
DD
CL1
latch clock
(
)
shift clock
(
)
CL2
shift clock
(
)
latch clock
(
)
M
polarity
M
_
M
CL1,CL2
(32,33)
FCS
(43)
Input
Input
Shift/latch clock of display data and polarity of M signal
are changed by FCS signal.
By setting FCS to V
DD
level , user can select the function
that use Part 1 as segment driver and Part 2 as common
driver simultaneously.
NC(39)
No connection pin
N.C
IN T E G R A L
4
INTEGRAL [ INTEGRAL CORP. ]
