TECHNICAL DATA
IW4040B
12-Stage Binary Ripple Counter
High-Voltage Silicon-Gate CMOS
The IW4040B is ripple-carry binary counter. All counter stages are
master-slave flip-flops. The state of a counter advances one count on the
negative transition of each input pulse; a high level on the RESET line resets
the counter to its all zeros state. Schmitt trigger action on the input-pulse
line permits unlimited rise and fall times.
•
•
•
Operating Voltage Range: 3.0 to 18 V
Maximum input current of 1
µA
at 18 V over full package-temperature
range; 100 nA at 18 V and 25°C
Noise margin (over full package temperature range):
1.0 V min @ 5.0 V supply
2.0 V min @ 10.0 V supply
2.5 V min @ 15.0 V supply
N SUFFIX
PLASTIC DIP
16
1
16
1
ORDERING INFORMATION
IW4040BN
IW4040BD
IZ4040B
Plastic DIP
SOIC
chip
T
A
= -55° to 125° C
for all packages
LOGIC DIAGRAM
9
Q1
7
Q2
6
Q3
CLOCK
10
5
3
2
4
13
12
14
15
1
Q12
11
RESET
Q4
Q5
Q6
Q7
Q8
Q9
Q10
Q11
Q12
Q6
Q5
Q7
Q4
Q3
Q2
GND
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V CC
Q11
Q10
Q8
Q9
RESET
CLOCK
Q1
PIN ASSIGNMENT
FUNCTION TABLE
Inputs
Clock
Reset
L
L
X
H= high level
L = low level
X=don’t care
H
Output
Output state
No change
Advance to next
state
All Outputs are low
PIN 16 =V
CC
PIN 8 = GND
INTEGRAL
1
INTEGRAL [ INTEGRAL CORP. ]
