8088
ing the direction of the bus during read operations. In
the event that a ‘‘NOT READY’’ indication is given
by the addressed device, ‘‘wait’’ states (Tw) are in-
serted between T3 and T4. Each inserted ‘‘wait’’
state is of the same duration as a CLK cycle. Periods
can occur between 8088 driven bus cycles. These
are referred to as ‘‘idle’’ states (Ti), or inactive CLK
cycles. The processor uses these cycles for internal
housekeeping.
which use register DX as a pointer, have full address
capability, while the direct I/O instructions directly
address one or two of the 256 I/O byte locations in
page 0 of the I/O address space. I/O ports are ad-
dressed in the same manner as memory locations.
Designers familiar with the 8085 or upgrading an
8085 design should note that the 8085 addresses
I/O with an 8-bit address on both halves of the 16-
bit address bus. The 8088 uses a full 16-bit address
on its lower 16 address lines.
During T1 of any bus cycle, the ALE (address latch
enable) signal is emitted (by either the processor or
the 8288 bus controller, depending on the MN/MX
strap). At the trailing edge of this pulse, a valid ad-
dress and certain status information for the cycle
may be latched.
EXTERNAL INTERFACE
Processor Reset and Initialization
Status bits S0, S1, and S2 are used by the bus con-
troller, in maximum mode, to identify the type of bus
transaction according to the following table:
Processor initialization or start up is accomplished
with activation (HIGH) of the RESET pin. The 8088
RESET is required to be HIGH for greater than four
clock cycles. The 8088 will terminate operations on
the high-going edge of RESET and will remain dor-
mant as long as RESET is HIGH. The low-going
transition of RESET triggers an internal reset se-
quence for approximately 7 clock cycles. After this
interval the 8088 operates normally, beginning with
the instruction in absolute locations FFFF0H (See
Figure 4). The RESET input is internally synchroniz-
ed to the processor clock. At initialization, the HIGH
to LOW transition of RESET must occur no sooner
than 50 ms after power up, to allow complete initiali-
zation of the 8088.
S2
S1
S0
Characteristics
0(LOW)
0
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Interrupt Acknowledge
Read I/O
Write I/O
0
0
1(HIGH)
Halt
Instruction Fetch
Read Data from Memory
Write Data to Memory
Passive (No Bus Cycle)
1
1
1
Status bits S3 through S6 are multiplexed with high
order address bits and are therefore valid during T2
through T4. S3 and S4 indicate which segment reg-
ister was used for this bus cycle in forming the ad-
dress according to the following table:
NMI asserted prior to the 2nd clock after the end of
RESET will not be honored. If NMI is asserted after
that point and during the internal reset sequence,
the processor may execute one instruction before
responding to the interrupt. A hold request active
immediately after RESET will be honored before the
first instruction fetch.
S
4
S
Characteristics
3
0(LOW)
0
0
Alternate Data (Extra Segment)
Stack
All 3-state outputs float to 3-state OFF during
RESET. Status is active in the idle state for the first
clock after RESET becomes active and then floats
to 3-state OFF. ALE and HLDA are driven low.
1
0
1
1(HIGH)
1
Code or None
Data
S5 is a reflection of the PSW interrupt enable bit. S6
is always equal to 0.
Interrupt Operations
Interrupt operations fall into two classes: software or
hardware initiated. The software initiated interrupts
and software aspects of hardware interrupts are
specified in the instruction set description in the
iAPX 88 book or the iAPX 86,88 User’s Manual.
Hardware interrupts can be classified as nonmaska-
ble or maskable.
I/O Addressing
In the 8088, I/O operations can address up to a
maximum of 64K I/O registers. The I/O address ap-
pears in the same format as the memory address on
bus lines A15–A0. The address lines A19–A16 are
zero in I/O operations. The variable I/O instructions,
11
INTEL [ INTEL ]
