Networking Silicon — 82551IT
The 82551IT supports PCI interface standards. In the PCI mode, it is five volts tolerant and
supports both 5 V and 3.3 V signaling environments.
Table 47. PCI Interface DC Specifications
Symbol
Parameter
Condition
Min
Max
Units
Notes
V
IHP
V
ILP
V
IPUP
V
IPDP
I
ILP
V
OHP
V
OLP
C
INP
C
CLKP
C
IDSEL
L
PINP
I
OFFPME
Input High Voltage
Input Low Voltage
Input Pull-up Voltage
Input Pull-down Voltage
Input Leakage Current
Output High Voltage
Output Low Voltage
Input Pin Capacitance
CLK Pin Capacitance
IDSEL Pin Capacitance
Pin Inductance
PME# Input Leakage
Current
V
O
< V
IO
0 < V
IN
< V
CC
I
out
= -2 mA
I
out
= -500 µA
I
out
= 3 mA, 6 mA
I
out
= 1500 µA
0.475V
CC
-0.5
0.7V
CC
V
IO
+ 0.5
0.325V
CC
V
V
V
1
1
2
PCI
3, PCI
4
4
4
4
5
0.2V
CC
±10
2.4
0.9V
CC
0.55
0.1V
CC
10
5
12
8
20
1
V
µA
V
V
V
V
pF
pF
pF
nH
mA
NOTES:
1. These values are only applicable in 3.3 V signaling environments. Outside of this limit the input buffer must
consume its minimum current.
2. Input leakage currents include high-Z output leakage for all bidirectional buffers with tristate outputs.
3. Signals without pull-up resistors have 3 mA low output current; and signals requiring pull-up resistors, 6 mA.
The signals requiring pull-up resistors include: FRAME#, TRDY#, IRDY#, DEVSEL#, STOP#, SERR# and
PERR#.
4. This value is characterized but not tested.
5. This input leakage current is the maximum allowable leakage into the PME# open drain driver when power is
removed from V
CC
of the component. This assumes that no event has occurred to cause the device to
assertion of PME#.
Table 48. Flash/EEPROM Interface DC Specifications
Symbol
Parameter
Condition
Min
Max
Units
Notes
V
IHL
V
ILL
I
ILL
V
OHL
V
OLL
C
INL
Input High Voltage
Input Low Voltage
Input Low Leakage
Current
Output High Voltage
Output Low Voltage
Input Pin Capacitance
0 < V
IN
< V
CC
I
out
= -1 mA
I
out
= 2 mA
2.0
-0.5
V
CC
+ 0.5
0.8
±20
V
V
µA
V
2.4
0.4
10
V
pF
1
1. This value is characterized but not tested.
Datasheet
77
INTEL [ INTEL CORPORATION ]
