28F320J5 and 28F640J5
Revision History
Date of
Version
Revision
Description
09/01/97
09/17/97
12/01/97
-001
-002
-003
Original version
Modifications made to cover sheet
/GND Pins Converted to No Connects Specification Change added
V
CC
I
, I
, I
and I
Specification Change added
CCE
CCS CCD CCW
Order Codes Specification Change added
01/31/98
03/23/98
-004
-005
The µBGA* chip-scale package in Figure 2 was changed to a 52-ball package
and appropriate documentation added. The 64-Mb µBGA package dimensions
were changed in Figure 2. Changed Figure 4 to read SSOP instead of TSOP.
32-Mbit Intel StrataFlash memory read access time added. The number of
block erase cycles was changed. The write buffer program time was changed.
The operatingtemperature was changed. A read parameter was added. Sev-
eral program, erase, and lock-bit specifications were changed. Minor docu-
mentation changes were made as well. Datasheet designation changed from
Advance Information to Preliminary.
07/13/98
12/01/98
-006
-007
Intel StrataFlash memory 32-Mbit µBGA package removed. t
read specifi-
EHEL
cation reduced. Table 4 was modified. The Ordering Information was updated.
Removed 32 Mbit, 100 ns references and orderinginformation for same. Pro-
vided clearer V
specifications. Provided maximum program/erase specifica-
OH
tion. Added Input Signal Transitions—Reducing Overshoots and Undershoots
When Using Buffers/Transceivers to Design Considerations section.
Name of document changed from Intel® StrataFlash™ Memory Technology 32
and 64 Mbit.
05/04/99
09/16/99
-008
-009
Updated CFI Tables, Section 4.2.1—Section 4.2.7.
OperatingTemperature Range Specification was increased to –20 °C to
+85° C. The 32-Mbit Read Access at +85 °C was changed (Section 6.5, AC
Characteristics-Read Only Operations).
10/20/99
-010
Modified Write Pulse Width definition
Added lock-bit default status (Section 4.11)
Added order code information for –20 °C to +85 °C
11/08/99
12/16/99
-011
-012
Modified Chip Enable Truth Table
Corrected error in command table
Removed erase queuingoption from Figure 9, Block Erase Flowchart
06/26/00
-013
Add reference to 0.25 micron process on cover page
Corrected error in Table 10, Maximum buffer write time.
Updated section 6.7 program/erase times.
Corrected error in table 19 maximum temperature range
03/28/01
04/23/02
-014
-015
Changed Clear Block-Lock Bit Time in Section 6.7.
Added .25 micron ETOXVI process technology ordering information
Removed µBGA CSP information
Datasheet
5
INTEL [ INTEL ]
