BYTE-WIDE SMART 3 FlashFile™ MEMORY FAMILY
To protect programmed data, each block can be
locked. This block locking mechanism uses a
combination of bits, block lock-bits and a master
lock-bit, to lock and unlock individual blocks. The
block lock-bits gate block erase and program
operations, while the master lock-bit gates block
lock-bit configuration operations. Lock-bit config-
uration operations (Set Block Lock-Bit, Set Master
Lock-Bit, and Clear Block Lock-Bits commands) set
and clear lock-bits.
The status register and RY/BY# output indicate
whether or not the device is busy executing or
ready for a new command. Polling the status
register, system software retrieves WSM feedback.
The RY/BY# output gives an additional indicator of
WSM activity by providing a hardware status signal.
Like the status register, RY/BY#-low indicates that
the WSM is performing a block erase, program, or
lock-bit configuration operation. RY/BY#-high
indicates that the WSM is ready for a new
command, block erase is suspended, program is
suspended, or the device is in deep power-down
mode.
The Automatic Power Savings (APS) feature
substantially reduces active current when the
device is in static mode (addresses not switching).
In APS mode, the typical I
CCR
current is 3 mA.
When CE# and RP# pins are at V
CC
, the
component enters a CMOS standby mode. Driving
RP# to GND enables a deep power-down mode
which significantly reduces power consumption,
provides write protection, resets the device, and
clears the status register. A reset time (t
PHQV
) is
required from RP# switching high until outputs are
valid. Likewise, the device has a wake time (t
PHEL
)
from RP#-high until writes to the CUI are
recognized.
E
1.3
Pinout and Pin Description
The family of devices is available in 40-lead TSOP
(Thin Small Outline Package, 1.2 mm thick), 44-
lead PSOP (Plastic Small Outline Package) and 40-
bump
µBGA*
CSP (28F008S3 and 28F016S3 only).
Pinouts are shown in Figures 2, 3 and 4.
DQ
0
- DQ
7
Output
Buffer
Input
Buffer
Identifier
Register
Status
Register
Command
Register
I/O Logic
V
CC
CE#
WE#
OE#
RP#
Data
Comparator
4-Mbit: A
0
- A
18
,
8-Mbit: A
0
- A
19
,
16-Mbit: A
0
- A
20
Input
Buffer
Y
Decoder
Y Gating
Write State
Machine
RY/BY#
Program/Erase
Voltage Switch
V
PP
Address
Latch
X
Decoder
4-Mbit: Eight
8-Mbit: Sixteen
16-Mbit: Thirty-Two
64-Kbyte Blocks
V
CC
GND
Address
Counter
Figure 1. Block Diagram
6
PRELIMINARY
INTEL [ INTEL CORPORATION ]
