28F020
E
DQ
0
- DQ
7
V
CC
V
SS
V
PP
Erase Voltage
Switch
To Array Source
Input/Output
Buffers
WE#
State
Control
Command
Register
Integrated Stop
Timer
PGM Voltage
Switch
CE#
OE#
Chip Enable
Output Enable
Logic
STB
Data Latch
STB
Address Latch
Y-Decoder
Y-Gating
A
0
- A
17
X-Decoder
2,097,152 Bit
Cell Matrix
0245_01
Figure 1. 28F020 Block Diagram
Table 1. Pin Description
Symbol
A
0
–A
17
DQ
0
–DQ
7
Type
INPUT
INPUT/OUTPUT
Name and Function
ADDRESS INPUTS
for memory addresses. Addresses are
internally latched during a write cycle.
DATA INPUT/OUTPUT:
Inputs data during memory write cycles;
outputs data during memory read cycles. The data pins are active
high and float to tri-state
off
when the chip is deselected or the
outputs are disabled. Data is internally latched during a write cycle.
CHIP ENABLE:
Activates the device’s control logic, input buffers,
decoders and sense amplifiers. CE# is active low; CE# high
deselects the memory device and reduces power consumption to
standby levels.
OUTPUT ENABLE:
Gates the devices output through the data
buffers during a read cycle. OE# is active low.
WRITE ENABLE:
Controls writes to the control register and the
array. Write enable is active low. Addresses are latched on the
falling edge and data is latched on the rising edge of the WE#
pulse.
Note:
With V
PP
≤
6.5 V, memory contents cannot be altered.
ERASE/PROGRAM POWER SUPPLY
for writing the command
register, erasing the entire array, or programming bytes in the array.
DEVICE POWER SUPPLY
(5 V ±10%)
GROUND
CE#
INPUT
OE#
WE#
INPUT
INPUT
V
PP
V
CC
V
SS
6
INTEL [ INTEL CORPORATION ]
