4-MBIT (256K X 16 512K X 8)
BOOT BLOCK
FLASH MEMORY FAMILY
28F400BX-T B 28F004BX-T B
Y
x8 x16 Input Output Architecture
28F400BX-T 28F400BX-B
For High Performance and High
Integration 16-bit and 32-bit CPUs
x8-only Input Output Architecture
28F004BX-T 28F004BX-B
For Space Constrained 8-bit
Applications
Upgradeable to Intel’s Smart Voltage
Products
Optimized High-Density Blocked
Architecture
One 16-KB Protected Boot Block
Two 8-KB Parameter Blocks
One 96-KB Main Block
Three 128-KB Main Blocks
Top or Bottom Boot Locations
Extended Cycling Capability
100 000 Block Erase Cycles
Automated Word Byte Write and Block
Erase
Command User Interface
Status Registers
Erase Suspend Capability
SRAM-Compatible Write Interface
Automatic Power Savings Feature
1 mA Typical I
CC
Active Current in
Static Operation
Y
Very High-Performance Read
60 80 120 ns Maximum Access Time
30 40 40 ns Maximum Output Enable
Time
Low Power Consumption
20 mA Typical Active Read Current
Reset Deep Power-Down Input
0 2
mA
I
CC
Typical
Acts as Reset for Boot Operations
Extended Temperature Operation
b
40 C to
a
85 C
Write Protection for Boot Block
Hardware Data Protection Feature
Erase Write Lockout During Power
Transitions
Industry Standard Surface Mount
Packaging
28F400BX JEDEC ROM Compatible
44-Lead PSOP
56-Lead TSOP
28F004BX 40-Lead TSOP
12V Word Byte Write and Block Erase
V
PP
e
12V
g
5% Standard
V
PP
e
12V
g
10% Option
ETOX
TM
III Flash Technology
5V Read
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
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Information in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or
copyright for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products Intel retains the right to make
changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata
COPYRIGHT
INTEL CORPORATION 1995
November 1995
Order Number 290451-005