28F004/400B3, 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
Revision History
Number
-001
Original version
Section 3.4,
V
PP
Program and Erase Voltages,
added
Updated Figure 9:
Automated Block Erase Flowchart
Updated Figure 10:
Erase Suspend/Resume Flowchart
(added program to table)
Updated Figure 16:
AC Waveform: Program and Erase Operations
(updated notes)
I
PPR
maximum specification change from ±25
µA
to ±50
µA
Program and Erase Suspend Latency specification change
Updated Appendix A:
Ordering Information
(included 8 M and 4 M information)
Updated Figure, Appendix D:
Architecture Block Diagram
(Block info. in words not bytes)
Minor wording changes
Combined byte-wide specification (previously 290605) with this document
Improved speed specification to 80 ns (3.0 V) and 90 ns (2.7 V)
Improved 1.8 V I/O option to minimum 1.65 V (Section 3.4)
Improved several DC characteristics (Section 4.4)
Improved several AC characteristics (Sections 4.5 and 4.6)
Combined 2.7 V and 1.8 V DC characteristics (Section 4.4)
Added 5 V V
PP
read specification (Section 3.4)
Removed 120 ns and 150 ns speed offerings
Moved
Ordering Information
from Appendix to Section 6.0; updated information
Moved
Additional Information
from Appendix to Section 7.0
Updated figure Appendix B,
Access Time vs. Capacitive Load
Updated figure Appendix C,
Architecture Block Diagram
Moved Program and Erase Flowcharts to Appendix E
Updated
Program Flowchart
Updated
Program Suspend/Resume Flowchart
Minor text edits throughout
Added 32-Mbit density
Added 98H as a reserved command (Table 4)
A
1
–A
20
= 0 when in read identifier mode (Section 3.2.2)
Status register clarification for SR3 (Table 7)
V
CC
and V
CCQ
absolute maximum specification = 3.7 V (Section 4.1)
Combined I
PPW
and I
CCW
into one specification (Section 4.4)
Combined I
PPE
and I
CCE
into one specification (Section 4.4)
Max Parameter Block Erase Time (t
WHQV2
/t
EHQV2
) reduced to 4 sec (Section 4.7)
Max Main Block Erase Time (t
WHQV3
/t
EHQV3
) reduced to 5 sec (Section 4.7)
Erase suspend time @ 12 V (t
WHRH2
/t
EHRH2
) changed to 5 µs typical and 20 µs maximum
(Section 4.7)
Ordering Information
updated (Section 6.0)
Write State Machine Current/Next States Table updated (Appendix A)
Program Suspend/Resume Flowchart updated (Appendix F)
Erase Suspend/Resume Flowchart updated (Appendix F)
Text clarifications throughout
µBGA
package diagrams corrected (Figures 3 and 4)
I
PPD
test conditions corrected (Section 4.4)
32-Mbit ordering information corrected (Section 6)
µBGA
package top side mark information added (Section 6)
V
IH
and V
IL
Specification change (Section 4.4)
I
CCS
test conditions clarification (Section 4.4)
Added Command Sequence Error Note (Table 7)
Datasheet renamed from
Smart 3 Advanced Boot Block 4-Mbit, 8-Mbit, 16-Mbit Flash
Memory Family.
Added device ID information for 4-Mbit x8 device
Removed 32-Mbit x8 to reflect product offerings
Minor text changes
Corrected RP# pin description in Table 2,
3 Volt Advanced Boot Block Pin Descriptions
Corrected typographical error fixed in
Ordering Information
Description
-002
-003
-004
-005
-006
-007
3UHOLPLQDU\
v
INTEL [ INTEL CORPORATION ]
