8XC196MD
PROCESS INFORMATION
This device is manufactured on PX29.5, a CHMOS
III-E process. Additional process and reliability infor-
mation is available in the
Intel
®
Quality System
Handbook.
Table 2. 8XC196MD Memory Map
Description
External Memory or I/O
Internal ROM/EPROM or External
Memory (Determined by EA)
Reserved. Must contain FFH.
(Note 5)
PTS Vectors
Upper Interrupt Vectors
ROM/EPROM Security Key
272323 – 2
Address
0FFFFH
06000H
5FFFH
2080H
207FH
205EH
205DH
2040H
203FH
2030H
202FH
2020H
201FH
201CH
201BH
201AH
2019H
2018H
2017H
2014H
2013H
2000H
1FFFH
1F00H
1EFFH
0200H
01FFH
0018H
0017H
0000H
x
x
Reserved. Must contain FFH.
(Note 5)
Reserved. Must Contain 20H
(Note 5)
NOTE:
EPROMs are available as One Time Programmable
(OTPROM) only.
CCB1
Reserved. Must Contain 20H
(Note 5)
CCB0
Reserved. Must contain FFH.
(Note 5)
Lower Interrupt Vectors
SFR’s
External Memory
488 Bytes Register RAM (Note 1)
CPU SFR’s (Notes 1. 3)
Figure 2. The 8XC196MD Family Nomenclature
Table 1. Thermal Characteristics
Package
Type
PLCC
QFP
θ
ja
35
°
C/W
56
°
C/W
θ
jc
13
°
C/W
12
°
C/W
All thermal impedance data is approximate for static air
conditions at 1W of power dissipation. Values will change
depending on operation conditions and application. See
the Intel
Packaging Handbook
(order number 240800) for a
description of Intel’s thermal impedance test methodology.
NOTES:
1. Code executed in locations 0000H to 01FFH will be
forced external.
2. Reserved memory locations must contain 0FFH unless
noted.
3. Reserved SFR bit locations must contain 0.
4. Refer to 8XC196MC for SFR descriptions.
5. WARNING: Reserved memory locations must not be
written or read. The contents and/or function of these lo-
cations may change with future revisions of the device.
Therefore, a program that relies on one or more of these
locations may not function properly.
3
INTEL [ INTEL CORPORATION ]
