UPI-C42 UPI-L42
Table 1 Pin Description
Symbol
TEST 0
TEST 1
DIP
Pin
No
1
39
PLCC
Pin
No
2
43
QFP
Pin
No
18
16
Type
I
Name and Function
TEST INPUTS
Input pins which can be directly tested using conditional
branch instructions
FREQUENCY REFERENCE
TEST 1 (T
1
) functions as the event timer
input (under software control) TEST 0 (T
0
) is a multi-function pin used
during PROM programming and ROM EPROM verification during Sync
Mode to reset the instruction state to S1 and synchronize the internal clock
to PH1
XTAL 1
XTAL 2
RESET
2
3
4
3
4
5
19
20
22
O
I
I
OUTPUT
Output from the oscillator amplifier
INPUT
Input to the oscillator amplifier and internal clock generator
circuits
RESET
Input used to reset status flip-flops set the program counter to
zero and force the UPI-C42 from the suspend power down mode
RESET is also used during EPROM programming and verification
SS
5
6
23
I
SINGLE STEP
Single step input used in conjunction with the SYNC output
to step the program through each instruction (EPROM) This should be tied
to
a
5V when not used This pin is also used to put the device in Sync
Mode by applying 12 5V to it
CHIP SELECT
Chip select input used to select one UPI microcomputer
out of several connected to a common data bus
EXTERNAL ACCESS
External access input which allows emulation
testing and ROM EPROM verification This pin should be tied low if
unused
READ
I O read input which enables the master CPU to read data and
status words from the OUTPUT DATA BUS BUFFER or status register
COMMAND DATA SELECT
Address Input used by the master processor
to indicate whether byte transfer is data (A
0
e
0 F1 is reset) or command
(A
0
e
1 F1 is set) A
0
e
0 during program and verify operations
WRITE
I O write input which enables the master CPU to write data and
command words to the UPI INPUT DATA BUS BUFFER
OUTPUT CLOCK
Output signal which occurs once per UPI instruction
cycle SYNC can be used as a strobe for external circuitry it is also used to
synchronize single step operation
DATA BUS
Three-state bidirectional DATA BUS BUFFER lines used to
interface the UPI microcomputer to an 8-bit master system data bus
PORT 1
8-bit PORT 1 quasi-bidirectional I O lines P
10
– P
17
access the
signature row and security bit
CS
EA
6
7
7
8
24
25
I
I
RD
A
0
8
9
9
10
26
27
I
I
WR
SYNC
10
11
11
13
28
29
I
O
D
0
–D
7
(BUS)
P
10
–P
17
12–19
27–34
14–21
30–33
35–38
30–37
2– 10
I O
I O
2
INTEL [ INTEL CORPORATION ]
