3 Volt Intel® Advanced+ Boot Block Flash Memory Stacked-CSP Family
Table 12. DC Characteristics
2.7 V – 3.3 V
Symbol
Parameter
Device
Note
Units
Test Conditions
Min
Max
Flash/
SRAM
V
Input Low Voltage
–0.2
0.6
V
V
IL
Flash/
SRAM
V
CC
+0.2
V
Input High Voltage
Output Low Voltage
2.3
IH
F-V /S-V = V Min
Flash/
SRAM
CC
CC
CC
V
–0.10
0.10
V
V
OL
I
= 100 µA
OL
F-V /S-V = V Min
Flash/
SRAM
V
–
CC
CC
CC
CC
V
Output High Voltage
OH
0.1
I
= –100 µA
OH
V
V
V
V
V
F-V Lock-Out Voltage
Flash
Flash
1
1
1.0
3.3
V
V
Complete Write Protection
PPLK
PP
F-V during Program / Erase
1.65
11.4
1.5
PP1
PP
Operations
1,2
12.6
PP2
V
Prog/Erase Lock Voltage
Flash
Flash
V
V
LKO
LKO2
CC
V
Prog/Erase Lock Voltage
1.2
CCQ
NOTES:
1. Erase and Program are inhibited when F-V < V
and not guaranteed outside the valid F-V ranges of V
and V
.
PP2
pp
PPLK
pp
PP1
2. Applying F-V = 11.4V–12.6V during program/erase can only be done for a maximum of 1000 cycles on the main blocks and
pp
2500 cycles on the parameter blocks. F-V may be connected to 12 V for a total of 80 hours maximum. See Section 4.2.1 for
pp
details.
Figure 4. Input/Output Reference Waveform
VCC
VCC
2
VCC
2
TEST POINTS
INPUT
OUTPUT
0.0
NOTE: AC test inputs are driven at V
for a logic “1” and 0.0V for a logic “0.” Input timing begins, and output
CCQ
timing ends, at V
/2. Input rise and fall times (10%–90%) <10 ns. Worst case speed conditions are
CCQ
when V
= V
Min.
CCQ
CCQ
0645_07
Figure 5. Test Configuration
Device
Under Test
Out
CL
0666_05
NOTE: C includes jig capacitance.
L
28
Datasheet
INTEL [ INTEL ]
