8XC196KB 8XC196KB16
AC CHARACTERISTICS
(Continued)
Test Conditions Capacitive load on all pins
e
100 pF Rise and fall times
e
10 ns F
OSC
e
12 16 MHz
The 87C196KB will meet these specifications
Symbol
F
XTAL
F
XTAL
T
OSC
T
OSC
T
XHCH
T
CLCL
T
CHCL
T
CLLH
T
LLCH
T
LHLH
T
LHLL
T
AVLL
T
LLAX
T
LLRL
T
RLCL
T
RLRH
T
RHLH
T
RLAZ
T
LLWL
T
CLWL
T
QVWH
T
CHWH
T
WLWH
T
WHQX
T
WHLH
T
WHBX
T
RHBX
T
WHAX
T
RHAX
Description
Frequency on XTAL1
12 MHz
Frequency on XTAL1
16 MHz
1 F
XTAL
12 MHz
1 F
XTAL
16 MHz
XTAL1 High to CLKOUT High or Low
CLKOUT Cycle Time
CLKOUT High Period
CLKOUT Falling Edge to ALE Rising
ALE Falling Edge to CLKOUT Rising
ALE Cycle Time
ALE High Period
Address Setup to ALE Falling Edge
Address Hold after ALE Falling Edge
ALE Falling Edge to RD Falling Edge
RD Low to CLKOUT Falling Edge
RD Low Period
RD Rising Edge to ALE Rising Edge
RD Low to Address Float
ALE Falling Edge to WR Falling Edge
CLKOUT Low to WR Falling Edge
Data Stable to WR Rising Edge
CLKOUT High to WR Rising Edge
WR Low Period
Data Hold after WR Rising Edge
WR Rising Edge to ALE Rising Edge
BHE INST HOLD after WR Rising Edge
BHE INST HOLD after RD Rising Edge
AD8 – 15 hold after WR Rising Edge
AD8 – 15 hold after RD Rising Edge
T
OSC
b
10
0
T
OSC
b
23
b
5
a
15
a
25
Min
35
35
83 3
62 5
a
20
Max
12 0
16 0
286
286
a
110
Units
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
(Note 2)
(Note 2)
2 T
OSC
T
OSC
b
10
b
10
b
15
T
OSC
a
10
a
10
a
15
4 T
OSC
T
OSC
b
10
T
OSC
b
20
T
OSC
b
40
T
OSC
b
35
a
4
a
25
(Note 3)
T
OSC
a
10
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
(Note 3)
(Note 3)
(Note 3)
(Note 1)
T
OSC
b
5
T
OSC
T
OSC
a
25
T
OSC
a
25
a
5
T
OSC
b
15
T
OSC
b
15
T
OSC
b
15
T
OSC
b
15
T
OSC
b
10
T
OSC
b
30
T
OSC
b
25
T
OSC
a
5
T
OSC
a
10
ns
ns
ns
ns
ns
(Note 1)
NOTES
1 Assuming back-to-back bus cycles
2 Testing performed at 3 5 MHz however the device is static by design and will typically operate below 1 Hz
3 When using wait states all 2 T
OSC
a
n where n
e
number of wait states
11
INTEL [ INTEL CORPORATION ]
