PD6710/’22 — ISA-to-PC-Card (PCMCIA) Controllers
In this mode,
Extension Control 2
register bit 3 is set to ‘1’, enabling the respective GPSTB pin to
function as a read strobe. Reads from the corresponding extended index 0Ah cause GPSTB to go
active (default active level is low) for the duration of the system’s IOR* pulse.
Note:
Data is still written to the shadowed
External Data
register on writes to Extended Index 0Ah but is
not visible.
13.3
GPSTB in Suspend Mode
GPSTB read and write strobes operate while the device is in suspend mode, but they are not
allowed when the device is in hardware-assisted ‘Super-Suspend’ mode (AEN held high while in
Suspend mode).
A clock to the PD6722 is not required for the external signal at GPSTB to occur, but shadowing of
write values in the internal register at Extended Index 0Ah requires that the PD67XX is not in
Suspend mode so there is an active internal clock for register writes.
94
Datasheet
INTEL [ INTEL CORPORATION ]
