E
PAGE
1.0 INTRODUCTION .............................................5
1.1 Smart 3 Advanced Boot Block Flash
Memory Enhancements ..............................5
1.2 Product Overview.........................................6
2.0 PRODUCT DESCRIPTION..............................6
2.1 Package Pinouts ..........................................6
2.2 Block Organization .....................................11
2.2.1 Parameter Blocks ................................11
2.2.2 Main Blocks .........................................11
3.0 PRINCIPLES OF OPERATION .....................11
3.1 Bus Operation ............................................12
3.1.1 Read....................................................13
3.1.2 Output Disable.....................................13
3.1.3 Standby ...............................................13
3.1.4 Deep Power-Down / Reset ..................13
3.1.5 Write....................................................13
3.2 Modes of Operation....................................14
3.2.1 Read Array ..........................................14
3.2.2 Read Identifier .....................................15
3.2.3 Read Status Register ..........................16
3.2.4 Program Mode.....................................16
3.2.5 Erase Mode .........................................17
3.3 Block Locking.............................................20
3.3.1 WP# = V
IL
for Block Locking................20
3.3.2 WP# = V
IH
for Block Unlocking ............20
3.4 V
PP
Program and Erase Voltages ..............20
3.4.1 V
PP
= V
IL
for Complete Protection .......20
SMART 3 ADVANCED BOOT BLOCK
CONTENTS
PAGE
3.5 Power Consumption ...................................20
3.5.1 Active Power .......................................21
3.5.2 Automatic Power Savings (APS) .........21
3.5.3 Standby Power ....................................21
3.5.4 Deep Power-Down Mode.....................21
3.6 Power-Up/Down Operation.........................21
3.6.1 RP# Connected to System Reset ........21
3.6.2 V
CC
, V
PP
and RP# Transitions .............21
3.7 Power Supply Decoupling ..........................22
4.0 ELECTRICAL SPECIFICATIONS..................23
4.1 Absolute Maximum Ratings ........................23
4.2 Operating Conditions..................................24
4.3 Capacitance ...............................................24
4.4 DC Characteristics .....................................25
4.5 AC Characteristics—Read Operations .......28
4.6 AC Characteristics—Write Operations........30
4.7 Program and Erase Timings .......................31
5.0 RESET OPERATIONS ..................................33
6.0 ORDERING INFORMATION..........................34
7.0 ADDITIONAL INFORMATION .......................36
APPENDIX A: Write State Machine
Current/Next States.....................................37
APPENDIX B: Access Time vs.
Capacitive Load...........................................38
APPENDIX C: Architecture Block Diagram ......39
APPENDIX D: Word-Wide Memory Map
Diagrams......................................................40
APPENDIX E: Byte Wide Memory Map
Diagrams......................................................43
APPENDIX F: Program and Erase Flowcharts .45
PRELIMINARY
3
INTEL [ INTEL CORPORATION ]
