E
28F020
Table 2. 28F020 Bus Operations
(1)
Mode
Read
VPP
A0
A0
X
A9
A9
X
CE# OE#
WE#
VIH
VIH
X
DQ0–DQ7
VPPL
VPPL
VPPL
VPPL
VIL
VIL
VIH
VIL
VIL
VIH
X
Data Out
Tri-State
Tri-State
Data = 89H
Output Disable
READ-
Standby
X
X
(3)
ONLY
Intelligent Identifier
(Mfr)(2)
VIL
VID
VIL
VIH
(3)
Intelligent Identifier
(Device)(2)
VPPL
VIH
VID
VIL
VIL
VIH
Data = BDH
Read
VPPH
VPPH
VPPH
VPPH
A0
X
A9
VIL
VIL
VIH
VIL
VIL
VIH
X
VIH
VIH
X
Data Out(4)
Tri-State
Tri-State
Data In(6)
READ/
WRITE
Output Disable
Standby(5)
Write
X
X
X
A0
A9
VIH
VIL
NOTES:
1. Refer to DC Characteristics. When VPP = VPPL memory contents can be read but not written or erased.
2. Manufacturer and device codes may also be accessed via a command register write sequence. Refer to Table 3. Al other
addresses low.
3.
VID is the intelligent identifier high voltage. Refer toDC Characteristics.
4. Read operations with VPP = VPPH may access array data or the intelligent identifier codes.
5. With VPP at high voltage, the standby current equals ICC + IPP (standby).
6. Refer to Table 3 for valid data-in during a write operation.
7. X can be VIL or VIH
.
The two step program/erase write sequence to the
command register provides additional software
write protection.
2.2
Write Protection
The command register is only active when VPP is
at high voltage. Depending upon the application,
the system designer may choose to make the VPP
power supply switchable—available only when
memory updates are desired. When VPP = VPPL
the contents of the register default to the Read
command, making the 28F020 read only
2.2.1
BUS OPERATIONS
Read
,
2.2.1.1
a
memory. In this mode, the memory contents
cannot be altered.
The 28F020 has two control functions, both of
which must be logically active, to obtain data at the
outputs. Chip Enable (CE#) is the power control
and should be used for device selection. Output
Enable (OE#) is the output control and should be
used to gate data from the output pins,
independent of device selection. Refer to AC read
timing waveforms.
Or, the system designer may choose to “hardwire”
V
PP, making the high voltage supply constantly
available. In this case, all command register
functions are inhibited whenever VCC is below the
write lockout voltage VLKO (see Power-Up/Down
Protection). The 28F020 is designed to
accommodate either design practice, and to
encourage optimization of the processor memory
interface.
When VPP is high (VPPH), the read operation can
be used to access array data, to output the
intelligent identifier codes, and to access data for
program/erase verification. When VPP is low (VPPL),
the read operation can only access the array data.
9
INTEL [ INTEL ]
