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MFLHP2805D 参数 Datasheet PDF下载

MFLHP2805D图片预览
型号: MFLHP2805D
PDF下载: 下载PDF文件 查看货源
内容描述: DC / DC转换器, 28伏特的输入 [DC/DC CONVERTERS 28 VOLT INPUT]
分类和应用: 转换器输入元件
文件页数/大小: 9 页 / 123 K
品牌: INTERPOINT [ INTERPOINT CORPORATION COMPANY ]
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F
EATURES
–55° to +100°C operation
19 to 40 VDC input
Fully Isolated
Magnetic feedback
Fixed frequency, 600 kHz typical
Topology – Single Ended Forward
80 V for up to 50 ms transient protection
Inhibit function – input and output
Sync function – input and output
Output trim on single output models
Indefinite short circuit protection
Remote sense on single output models
Up to 87% efficiency
Parallelable up to 228 watts
DC/DC C
ONVERTERS
28 V
OLT
I
NPUT
MFLHP SERIES
100 WATT
MODELS
VDC O
UTPUT
SINGLE
5
12
15
DUAL
±5
±12
±15
Size (max.): 3.005 x 1.505 x 0.400 inches (76.33 x 38.23 x 10.16 mm)
See Section B8, case U1, for dimensions.
Weight:
100 grams maximum
Screening: Standard or ES. See Section C2 for screening options,
see Section A5 for ordering information.
DESCRIPTION
The MFLHP Series™ 28 volt DC/DC converters are rated up to 100
watts output power over a –55° to +100°C temperature range with a
28 Vdc nominal input. On dual output models, up to 70% of the rated
output power can be drawn from either the positive or negative
outputs. Current sharing allows the units to be paralleled for total
power of up to 270 watts. The welded, hermetically sealed package
is only 3.005 x 1.505 x 0.400 inches, giving the series an overall
power density of up to 67 watts per cubic inch.
I
NHIBIT
The MFLHP Series converters have two TTL compatible inhibit
terminals (INH1 and INH2) that can be used to disable power
conversion, resulting in a very low quiescent input current. An open
collector TTL compatible low (<0.8 volts) is required between INH1
(pin 4) and Input Common (pin 2) to inhibit the converter. An open
collector TTL compatible low (<0.5 volts) is required between INH2
(pin 12) and Output Common (pin 8) to inhibit the converter. The
application of intermediate voltages to these pins (1.5 to 10.5 volts)
should be avoided.
D
ESIGN
F
EATURES
The MFLHP Series converters are switching regulators that use a
quasi-square wave, single ended forward converter design with a
constant switching frequency of 600 kHz.
Isolation between input and output circuits is provided with a trans-
former in the forward path and wide bandwidth magnetic coupling in
the feedback control loop. The MFLHP Series uses a unique dual
loop feedback technique that controls output current with an inner
feedback loop and output voltage with a cascaded voltage mode
feedback loop.
The additional secondary current mode feedback loop improves
transient response in a manner similar to primary current mode
control and allows for ease of paralleling.
Tight load regulation is achieved through a wide-bandwidth
magnetic feedback circuit. The output voltage on single MFLHP
models can be easily trimmed by adding an external resistor. (See
Figure 1 for voltage changes with different resistor values.)
C
URRENT
S
HARING
AND
P
ARALLEL
O
PERATION
Multiple MFLHP converters may be used in parallel to drive a
common load (see Figure 2). In this mode of operation the load
current is shared by two or three MFLHP converters. In current
sharing mode, one MFLHP converter is designated as a master. The
SLAVE pin (pin 11) of the master is left unconnected and the
MSTR/INH2 pin (pin 12) of the master is connected to the SLAVE
pin (pin 11) of the slave units. The units designated as slaves have
the MSTR/INH2 pin (pin 12) connected to the SNS RTN pin (pin 9).
Figure 2 shows the typical setup for two or three units in parallel.
Note that synchronizing the units together (though shown in the
figure) is not required for current sharing operation. A second slave
unit may be placed in parallel with a master and slave; this requires
the TRI pin (pin 3) of the master unit to be connected to the SNS
RTN pin (pin 9).
When paralleled, 76% of the total combined power ratings of the
MFLHP converters are available at the load. Overload and short
circuit performance are not adversely affected during parallel
operation.
B2-19