80C286/883
Waveforms
(Continued)
BUS CYCLE TYPE
V
CH
CLK
V
CL
PCLK
(SEE NOTE 1)
5
INTR, NMI
HOLD, PEREQ
(SEE NOTE 2)
4
ERROR, BUSY
(SEE NOTE 2)
4
CLK
5
RESET
19
19
RESET
φ1
T
X
φ2
CLK
V
CH
φ2
φ1
T
X
φ1
φ2
V
CL
7
6
(SEE NOTE 1)
V
CH
φ1
T
X
φ2
φ2
V
CL
7
6
(SEE NOTE 1)
NOTES:
1. PCLK indicates which processor cycle phase will occur on the
next CLK. PCLK may not indicate the correct phase until the first
cycle is performed.
2. These inputs are asynchronous. The setup and hold times shown
assure recognition for testing purposes.
FIGURE 3. 80C286/883 ASYNCHRONOUS INPUT SIGNAL
TIMING
BUS CYCLE TYPE
V
CH
CLK
V
CL
HILDA
16
(SEE NOTE 4)
12A (NOTE 3)
12B
PEACK
IF NPX TRANSFER
BHE, LOCK
A
23
- A
0
,
M/IO,
COD/INTA
13
(SEE NOTE 5)
VALID
14
D
15
- D
0
(SEE NOTE 6)
(SEE NOTE 2)
15
(SEE NOTE 1)
15
IF T
S
15
16
φ1
T
H
φ2
T
H
OR T
I
φ1
NOTE:
1. When RESET meets the setup time shown, the next CLK will
start or repeat
φ1
of a processor cycle.
FIGURE 4. 80C286/883 RESET INPUT TIMING AND SUBSE-
QUENT PROCESSOR CYCLE PHASE
T
I
T
H
φ2
φ1
φ2
φ1
φ2
S1 • S0
80C286/883
15
(SEE NOTE 3)
VALID IF WRITE
80C284
PCLK
NOTES:
1.
2.
3.
4.
5.
6.
These signals may not be driven by the 80C286/883 during the time shown. The worst case in terms of latest float time is shown.
The data bus will be driven as shown if the last cycle before T
I
in the diagram was a write T
C
.
The 80C286/883 puts its status pins in a high impedance logic one state during T
H
.
For HOLD request set up to HLDA, refer to Figure 8.
BHE and LOCK are driven at this time but will not become valid until T
S
.
The data bus will remain in a high impedance state if a read cycle is performed.
FIGURE 5. EXITING AND ENTERING HOLD
3-136
INTERSIL [ INTERSIL CORPORATION ]
