HS-0548RH, HS-0549RH
Schematic Diagrams
(Continued)
FROM
DECODE
+V
P
P
P
P
P
P
OVERVOLTAGE
V+
P
PROTECTION
N
N
A0 OR A0
A1 OR A1
A2 OR A2
N
N
N
R
11
IN
1K
D
6
D
7
Q
5
D
4
D
5
N
N
Q
6
OUT
N
N
V
V-
P
FROM
DECODE
ENABLE
TO N-CHANNEL DEVICE OF THE SWITCH PAIR
TO P-CHANNEL DEVICE OF THE SWITCH PAIR
FIGURE 5. ADDRESS DECODER
FIGURE 6. MULTIPLEX SWITCH
Burn-In/Life Test Circuits
V
1
F
0
F
3
V
1
D
1
C
1
1
2
3
4
5
6
R
1
7
8
16
15
14
13
12
11
10
9
D
2
C
2
V
2
F
1
F
2
V
2
D
1
C
1
1
2
3
4
5
6
R
1
7
8
16
15
14
13
12
11
10
9
D
2
C
2
V
3
HS-0548RH
DYNAMIC BURN-IN AND LIFE TEST CIRCUIT
V
1
V
2
R
1
C
1
D
1
F
0
F
1
F
2
F
3
=
=
=
=
=
=
=
=
=
-15V maximum, -16V minimum
+15V minimum, +16V maximum
10kΩ
±5%
1/4W
C
2
= 0.01µF minimum (per socket) or 0.1µF minimum
(per row)
D
2
= 1N4002 (or equivalent)
100kHz 50% duty cycle; V
IL
= 0.8V Max; V
IH
= 4.0V Min.
F
0/2
F
1/2
F
2/2
V
1
V
2
V
3
R
1
C
1
=
=
=
=
=
HS-0548RH
STATIC BURN-IN TEST CIRCUIT
5V minimum, 6V maximum
-15V maximum, -16V minimum
+15V minimum, +16V maximum
10kΩ
±5%
1/4W
C
2
= 0.01µF minimum (per socket) or 0.1µF minimum
(per row)
D
1
= D
2
= 1N4002 (or equivalent)
4
INTERSIL [ INTERSIL CORPORATION ]
