HIP6016
LUV
OVER
CURRENT
LATCH
OC1
S Q
R
0.15V
+
S
SOFT-START
COUNTER
R
SS
4V
+
UP
POR
OV
FAULT
LATCH
S Q
R
FAULT
INDUCTOR CURRENT
4V
2V
0V
OVERLOAD
APPLIED
VCC
INHIBIT
FAULT/RT
10V
0V
COUNT
=1
COUNT
=2
COUNT
=3
FAULT
REPORTED
-
-
FIGURE 7. FAULT LOGIC - SIMPLIFIED SCHEMATIC
latch. A sequence of three over-current fault signals also
sets the fault latch. A comparator indicates when C
SS
is fully
charged (UP signal), such that an under-voltage event on
either linear output (VSEN2 or VSEN3) is ignored until after
the soft-start interval (T4 in Figure 6). At start-up, this allows
V
OUT2
and V
OUT3
to slew up over increased time intervals.
Cycling the bias input voltage (+12V
IN
on the VCC pin) off
then on resets the counter and the fault latch.
0A
t0 t1
t2
TIME
t3
t4
FIGURE 8. OVER-CURRENT OPERATION
Over-Voltage Protection
During operation, a short on the upper PWM MOSFET (Q1)
causes V
OUT1
to increase. When the output exceeds the
over-voltage threshold of 115% (typical) of DACOUT, the
over-voltage comparator trips to set the fault latch and turns
Q2 on. This blows the input fuse and reduces V
OUT1
. The
fault latch raises the FAULT pin close to VCC potential.
A separate over-voltage circuit provides protection during
the initial application of power. For voltages on the VCC pin
below the power-on reset (and above ~4V), V
OUT1
is
monitored for voltages exceeding 1.26V. Should VSEN1
exceed this level, the lower MOSFET (Q2) is driven on.
soft-start voltage continues increasing to 4V before
discharging. The counter increments to 2. The soft-start cycle
repeats at T3 and trips the over-current comparator. The SS
pin voltage increases to 4V at T4 and the counter increments
to 3. This sets the fault latch to disable the converter. The fault
is reported on the FAULT pin.
The linear regulator operates in the same way as PWM to
over-current faults. Additionally, the linear regulator and
linear controller monitor the feedback pins for an under-
voltage. Should excessive currents cause VSEN2 or VSEN3
to fall below the linear under-voltage threshold, the LUV
signal sets the over-current latch if C
SS
is fully charged.
Blanking the LUV signal during the C
SS
charge interval allows
the linear outputs to build above the under-voltage threshold
during normal start-up. Cycling the bias input power off then
on resets the counter and the fault latch.
OVER-CURRENT TRIP: V
DS
> V
SET
(i
D
• r
DS(ON)
> I
OCSET
• R
OCSET
)
OCSET
I
OCSET
200µA
VCC
+
DRIVE
OC1
+
UGATE
PHASE
VCC
GATE
CONTROL
LGATE
PGND
V
PHASE
= V
IN
- V
DS
V
OCSET
= V
IN
- V
SET
V
DS
R
OCSET
V
SET
+
i
D
V
IN
= +5V
Over-Current Protection
All outputs are protected against excessive over-currents. The
PWM controller uses the upper MOSFET’s on-resistance,
r
DS(ON)
to monitor the current for protection against shorted
outputs. The linear regulator monitors the current of the
integrated power device and signals an over-current condition
for currents in excess of 180mA. Additionally, both the linear
regulator and the linear controller monitor VSEN2 and VSEN3
for under-voltage to protect against excessive currents.
Figures 8 and 9 illustrate the over-current protection with an
overload on OUT1. The overload is applied at T0 and the
current increases through the output inductor (L
OUT1
). At time
T1, the OVER-CURRENT1 comparator trips when the voltage
across Q1 (I
D
•
r
DS(ON)
) exceeds the level programmed by
R
OCSET
. This inhibits all outputs, discharges the soft-start
capacitor (C
SS
) with a 11µA current sink, and increments the
counter. C
SS
recharges at T2 and initiates a soft-start cycle
with the error amplifiers clamped by soft-start. With OUT1 still
overloaded, the inductor current increases to trip the over-
current comparator. Again, this inhibits all outputs, but the
OVER-
CURRENT1
PWM
HIP6016
-
FIGURE 9. OVER-CURRENT DETECTION
2-203
INTERSIL [ INTERSIL CORPORATION ]
