HIP6021A
error amplifier. Similarly, the COMP pin is the error amplifier
output. These pins are used to compensate the voltage-mode
control feedback loop of the synchronous PWM converter.
The AGP bus voltage (VOUT2) is set using the SELECT pin
to either a 1.5V linear regulated output or to the 3.3V
IN
through a pass device. Selection of either output voltage is
set depending on the logic level of the SELECT pin.
The two remaining linear controllers supply the 1.5V GTL
bus power (V
OUT3
) and the 1.8V memory power (V
OUT4
).
These output voltages are user adjustable. All linear
controllers are designed to employ an external pass
transistor.
VSEN1 (Pin 22)
This pin is connected to the PWM converter’s output voltage.
The PGOOD and OVP comparator circuits use this signal to
report output voltage status and for over-voltage protection.
DRIVE2 (Pin 1)
Connect this pin to the gate of an external MOSFET. This pin
provides the drive for the AGP regulator’s pass transistor.
Initialization
The HIP6021A automatically initializes upon receipt of input
power. Special sequencing of the input supplies is not
necessary. The Power-On Reset (POR) function continually
monitors the input supply voltages. The POR monitors the
bias voltage (+12V
IN
) at the VCC pin, the 5V input voltage
(+5V
IN
) on the OCSET pin, and the 3.3V input voltage
(+3.3V
IN
) at the VAUX pin. The normal level on OCSET is
equal to +5V
IN
less a fixed voltage drop (see over-current
protection). The POR function initiates soft-start operation
after all supply voltages exceed their POR thresholds.
VSEN2 (Pin 10)
Connect this pin to the output of the AGP linear regulator.
The voltage at this pin is regulated to the level
predetermined by the logic-level status of the SELECT pin.
This pin is also monitored for under-voltage events.
SELECT (Pin 11)
This pin determines the output voltage of the AGP bus linear
regulator. A low TTL input sets the output voltage to 1.5V
and the linear controller regulates this voltage to within
±3%.
A TTL high input turns Q3 on continuously, providing a DC
current path from the input (+3.3V
IN
) to the output (V
OUT2
)
of the AGP controller.
Soft-Start
The POR function initiates the soft-start sequence. Initially,
the voltage on the SS pin rapidly increases to approximately
1V (this minimizes the softstart interval). Then an internal
28µA current source charges an external capacitor (C
SS
) on
the SS pin to 4.5V. The PWM error amplifier reference input
(+ terminal) and output (COMP pin) are clamped to a level
proportional to the SS pin voltage. As the SS pin voltage
slews from 1V to 4V, the output clamp allows generation of
PHASE pulses of increasing width that charge the output
capacitor(s). After the output voltage increases to
approximately 70% of the set value, the reference input
clamp slows the output voltage rate-of-rise and provides a
smooth transition to the final set voltage. Additionally, all
linear regulators’ reference inputs are clamped to a voltage
proportional to the SS pin voltage. This method provides a
rapid and controlled output voltage rise.
Figure 2 shows the soft-start sequence for the typical
application. At T0 the SS voltage rapidly increases to
approximately 1V. At T1, the SS pin and error amplifier
output voltage reach the valley of the oscillator’s triangle
wave. The oscillator’s triangular waveform is compared to
the clamped error amplifier output voltage. As the SS pin
voltage increases, the pulse width on the PHASE pin
increases. The interval of increasing pulse width continues
until each output reaches sufficient voltage to transfer
control to the input reference clamp. If we consider the 2.5V
core output (V
OUT1
) in Figure 2, this time occurs at T2.
During the interval between T2 and T3, the error amplifier
reference ramps to the final value and the converter
regulates the output a voltage proportional to the SS pin
voltage. At T3 the input clamp voltage exceeds the
reference voltage and the output voltage is in regulation.
DRIVE3 (Pin 18)
Connect this pin to the gate of an external MOSFET. This pin
provides the drive for the 1.5V regulator’s pass transistor.
VSEN3 (Pin 19)
Connect this pin to the output of the 1.5V linear regulator.
This pin is monitored for under-voltage events.
DRIVE4 (Pin 15)
Connect this pin to the gate of an external MOSFET. This pin
provides the drive for the 1.8V regulator’s pass transistor.
VSEN4 (Pin 14)
Connect this pin to the output of the linear 1.8V regulator.
This pin is monitored for under voltage events.
Description
Operation
The HIP6021A monitors and precisely controls 4 output
voltage levels (Refer to Block and Simplified Power System
Diagrams, and Typical Application Schematic). It is designed
for microprocessor computer applications with 3.3V, 5V,
and 12V bias input from an ATX power supply. The
microprocessor core voltage (V
OUT1
) is controlled in a
synchronous-rectified buck converter configuration. The
PWM controller regulates the microprocessor core voltage
to a level programmed by the 5-bit digital-to-analog
converter (DAC).
7
INTERSIL [ INTERSIL CORPORATION ]
