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ICM7170IPG 参数 Datasheet PDF下载

ICM7170IPG图片预览
型号: ICM7170IPG
PDF下载: 下载PDF文件 查看货源
内容描述: 微处理器兼容,实时时钟 [Microprocessor-Compatible, Real-Time Clock]
分类和应用: 微处理器时钟
文件页数/大小: 13 页 / 81 K
品牌: INTERSIL [ INTERSIL CORPORATION ]
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ICM7170
August 1997
Microprocessor-Compatible, Real-Time Clock
Description
The ICM7170 real time clock is a microprocessor bus
compatible peripheral, fabricated using Intersil’s silicon gate
CMOS LSl process. An 8-bit bidirectional bus is used for the
data I/O circuitry. The clock is set or read by accessing the 8
internal separately addressable and programmable counters
from
1
/
100
seconds to years. The counters are controlled by
a pulse train divided down from a crystal oscillator circuit,
and the frequency of the crystal is selectable with the on-
chip command register. An extremely stable oscillator
frequency is achieved through the use of an on-chip
regulated power supply.
The device access time (t
ACC
) of 300ns eliminates the need
for wait states or software overhead with most
microprocessors. Furthermore, an ALE (Address Latch
Enable) input is provided for interfacing to microprocessors
with a multiplexed address/data bus. With these two special
features, the ICM7170 can be easily interfaced to any
available microprocessor.
The ICM7170 generates two types of interrupts, periodic and
alarm. The periodic interrupt (100Hz, 10Hz, etc.) can be
programmed by the internal interrupt control register to
provide 6 different output signals. The alarm interrupt is set
by loading an on-chip 51-bit RAM that activates an interrupt
output through a comparator. The alarm interrupt occurs
when the real time counter and alarm RAM time are equal. A
status register is available to indicate the interrupt source.
An on-chip Power Down Detector eliminates the need for
external components to support the battery back-up
function. When a power down or power failure occurs,
internal logic switches the on-chip counters to battery back-
up operation. Read/write functions become disabled and
operation is limited to time-keeping and interrupt generation,
resulting in low power consumption.
Internal latches prevent clock roll-over during a read cycle.
Counter data is latched on the chip by reading the
100th-seconds counter and is held indefinitely until the
counter is read again, assuring a stable and reliable time
value.
[ /Title
(ICM7
170)
/Sub-
ject
(Micro
proces-
sor-
Com-
pati-
ble,
Real-
Time
Clock)
/Autho
r ()
/Key-
words
(Inter-
sil
Corpo-
ration,
Real
Time
Clock,
Bat-
tery
Backu
p,
Inter-
nal
Oscil-
lator,
Micro-
proces-
sor
inter-
face,
Data
Features
• 8-Bit,
µP
Bus Compatible
- Multiplexed or Direct Addressing
• Regulated Oscillator Supply Ensures Frequency
Stability and Low Power
• Time From 1/100 Seconds to 99 Years
• Software Selectable 12/24 Hour Format
• Latched Time Data Ensures No Roll Over During Read
• Full Calendar with Automatic Leap Year Correction
• On-Chip Battery Backup Switchover Circuit
• Access Time Less than 300ns
• 4 Programmable Crystal Oscillator Frequencies Over
Industrial Temperature Range
• 3 Programmable Crystal Oscillator Frequencies Over
Military Temperature Range
• On-Chip Alarm Comparator and RAM
• Interrupts from Alarm and 6 Selectable Periodic
Intervals
• Standby Micro-Power Operation: 1.2µA Typical at 3.0V
and 32kHz Crystal
Applications
• Portable and Personal Computers
• Data Logging
• Industrial Control Systems
• Point Of Sale
Ordering Information
TEMP. RANGE
PART NUMBER
(
o
C)
ICM7170IPG
ICM7170IDG
ICM7170IBG
ICM7170MDG
ICM7170AIPG
ICM7170AIDG
ICM7170AIBG
ICM7170AMDG
NOTE:
-40 to 85
-40 to 85
-40 to 85
-55 to 125
-40 to 85
-40 to 85
-40 to 85
-55 to 125
PACKAGE
24 Ld PDIP
24 Ld SBDIP
24 Ld SOIC
24 Ld SBDIP
24 Ld PDIP
24 Ld SBDIP
24 Ld SOIC
24 Ld SBDIP
PKG.
NO.
E24.6
D24.6
M24.3
D24.6
E24.6
D24.6
M24.3
D24.6
“A” Parts Screened to <5µA I
STBY
at 32kHz.
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207
|
Copyright
©
Intersil Corporation 1999
File Number
3019.3
12-5