82C55A
tWOB
WR
tAOB
OBF
INTR
tWIT
ACK
tAK
OUTPUT
tWB
tAIT
FIGURE 9. MODE 1 (STROBED OUTPUT)
PA7-PA0
RD
CONTROL WORD
D7 D6 D5 D4 D3 D2 D1 D0
1
0
1
1
1/0
1
0
PC6, PC7
1 = INPUT
0 = OUTPUT
WR
PC4
PC5
PC3
PC6, PC7
PB7, PB0
PC1
PC2
PC0
8
STBA
IIBFA
INTRA
2
8
OBFB
ACKB
INTRB
I/O
WR
CONTROL WORD
D7 D6 D5 D4 D3 D2 D1 D0
1
0
1
0
1/0
1
1
PC4, PC5
1 = INPUT
0 = OUTPUT
RD
PA7-PA0
PC7
PC6
PC3
PC4, PC5
PB7, PB0
PC2
PC1
PC0
8
OBFA
ACKA
INTRA
2
I/O
8
STBB
IBFB
INTRB
PORT A - (STROBED INPUT)
PORT B - (STROBED OUTPUT)
PORT A - (STROBED OUTPUT)
PORT B - (STROBED INPUT)
Combinations of Mode 1: Port A and Port B can be individually defined as input or output in Mode 1 to support a wide variety of strobed I/O applications.
FIGURE 10. COMBINATIONS OF MODE 1
Operating Modes
Mode 2 (Strobed Bidirectional Bus I/O)
This functional configuration provides a means for
communicating with a peripheral device or structure on a
single 8-bit bus for both transmitting and receiving data
(bidirectional bus I/O). “Hand shaking” signals are provided to
maintain proper bus flow discipline similar to Mode 1. Interrupt
generation and enable/disable functions are also available.
Mode 2 Basic Functional Definitions:
• Used in Group A only
• One 8-bit, bidirectional bus Port (Port A) and a 5-bit
control Port (Port C)
• Both inputs and outputs are latched
• The 5-bit control port (Port C) is used for control and
status for the 8-bit, bidirectional bus port (Port A)
Output Operations
OBF
- (Output Buffer Full). The OBF output will go “low” to
indicate that the CPU has written data out to port A.
ACK
- (Acknowledge). A “low” on this input enables the three-
state output buffer of port A to send out the data. Otherwise,
the output buffer will be in the high impedance state.
INTE 1
- (The INTE flip-flop associated with OBF).
Controlled by bit set/reset of PC4.
Input Operations
STB
- (Strobe Input). A “low” on this input loads data into the
input latch.
IBF
- (Input Buffer Full F/F). A “high” on this output indicates
that data has been loaded into the input latch.
INTE 2
- (The INTE flip-flop associated with IBF). Controlled
by bit set/reset of PC4.
Bidirectional Bus I/O Control Signal Definition
(Figures 11, 12, 13, 14)
INTR
- (Interrupt Request). A high on this output can be
used to interrupt the CPU for both input or output operations.
11
FN2969.10
November 16, 2006
INTERSIL [ INTERSIL CORPORATION ]
