ISL6559
Most multi-phase controllers simply have the output voltage
fed back to the inverting input of the error amplifier through a
resistor. The ISL6559 features an internal differential
remote-sense amplifier in the feedback path. The amplifier
removes the voltage error encountered when measuring the
output voltage relative to the local controller ground
reference point, resulting in a more accurate means of
sensing output voltage. Connect the microprocessor sense
pins to the non-inverting input, VSEN, and inverting input,
RGND, of the remote-sense amplifier. The remote-sense
amplifier output, V
DIFF
, is then tied through an external
resistor to the inverting input of the error amplifier.
A digital to analog converter (DAC) generates a reference
voltage based on the state of logic signals at pins VID4
through VID0. The DAC decodes the a 5-bit logic signal
(VID) into one of the discrete voltages shown in Table 1.
Each VID input offers a 20µA pull-up to an internal 2.5V
source for use with open-drain outputs. External pull-up
resistors or active-high output stages can augment the pull-
up current sources, but a slight accuracy error can occur if
they are pulled above 2.9V. The DAC-selected reference
voltage is connected to the non-inverting input of the error
amplifier.
The ISL6559 features a second non-inverting input to the
error amplifier which allows the user to directly offset the
DAC reference voltage in the positive direction only. The
offset voltage is created by an internal current source which
EXTERNAL CIRCUIT
R
C
C
C
COMP
ERROR AMPLIFIER
FB
I
AVG
-
+
+
V
COMP
ISL6559 INTERNAL CIRCUIT
feeds out the OFS pin into a user selected external resistor
to ground. The resulting voltage across the resistor, V
OFS
, is
internally divided down by ten to create the offset voltage.
This method of offsetting the DAC voltage is more accurate
than external methods of level-shifting the FB pin.
TABLE 1. VOLTAGE IDENTIFICATION CODES
VID4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
VID3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
VID2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
VID1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
VID0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
DAC
1.550
1.525
1.500
1.475
1.450
1.425
1.400
1.375
1.350
1.325
1.300
1.275
1.250
1.225
1.200
1.175
1.150
1.125
1.100
1.075
1.050
1.025
1.000
0.975
0.950
0.925
0.900
0.875
0.850
0.825
0.800
Shutdown
+
R
FB
V
DROOP
-
IOUT
REFERENCE
VOLTAGE
VDIFF
1
1
1
REMOTE
SENSE
POINTS
V
OUT
VSEN
+
RGND
-
DIFFERENTIAL
REMOTE-SENSE
AMPLIFIER
OFS
1
1
1
1
1
1
1/10
100µA
OFFSET
VOLTAGE
GND
R
OFS
+
V
OFS
-
FIGURE 5. OUTPUT-VOLTAGE AND LOAD-LINE
REGULATION
The integrating compensation network shown in Figure 5
assures that the steady-state error in the output voltage is
limited to the error in the reference voltage (output of the
DAC) plus offset errors in the OFS current source, remote-
sense and error amplifiers. Intersil specifies the guaranteed
tolerance of the ISL6559 to include all variations in current
9
FN9084.8
December 29, 2004
INTERSIL [ INTERSIL CORPORATION ]
