January 2005
AS7C251MNTD32A
AS7C251MNTD36A
®
2.5V 1M × 32/36 Pipelined SRAM with NTDTM
Features
• Available in 100-pin TQFP packages
• Organization: 1,048,576 words × 32 or 36 bits
• NTD™architecture for efficient bus operation
• Fast clock speeds to 200 MHz
• Fast clock to data access: 3.2/3.5/3.8 ns
• Fast OE access time: 3.2/3.5/3.8 ns
• Fully synchronous operation
• Byte write enables
• Clock enable for operation hold
• Multiple chip enables for easy expansion
• 2.5V core power supply
• Self-timed write cycles
• Interleaved or linear burst modes
• Snooze mode for standby operation
• pipelined mode
• Common data inputs and data outputs
• Asynchronous output enable control
Logic block diagram
20
20
Q
A[19:0]
D
Address
register
Burst logic
CLK
D
Q
CE0
CE1
CE2
Write delay
addr. registers
20
CLK
R/W
BWa
Control
logic
CLK
BWb
BWc
BWd
ADV / LD
1M x 32/36
SRAM
LBO
ZZ
CLK
Array
32/36
32/36
DQ[a,b,c,d]
Data
Input
Register
D
Q
32/36
32/36
CLK
32/36
CLK
CEN
CLK
Output
Register
OE
32/36
OE
DQ[a,b,c,d]
Selection guide
-200
5
-166
6
-133
7.5
Units
ns
Minimum cycle time
Maximum clock frequency
Maximum clock access time
Maximum operating current
Maximum standby current
200
3.2
450
170
90
166
3.5
400
150
90
133
3.8
MHz
ns
350
140
90
mA
mA
mA
Maximum CMOS standby current (DC)
1/17/05, V 1.2
Alliance Semiconductor
P. 1 of 18
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