December 2004
AS7C251MNTF32A
AS7C251MNTF36A
®
2.5V 1M × 32/36 Flowthrough SRAM with NTDTM
Features
• Byte write enables
• Clock enable for operation hold
• Multiple chip enables for easy expansion
• 2.5V core power supply
• Self-timed write cycles
• Organization: 1,048,576 words × 32 or 36 bits
™
• NTD architecture for efficient bus operation
• Fast clock to data access: 7.5/8.5/10 ns
• Fast OE access time: 3.5/4.0 ns
• Fully synchronous operation
• Flow-through mode
• Asynchronous output enable control
• Available in 100-pin TQFP package
• Interleaved or linear burst modes
• Snooze mode for standby operation
Logic block diagram
20
20
A[19:0]
Q
D
Address
register
Burst logic
CLK
D
Q
CE0
CE1
CE2
Write delay
addr. registers
CLK
20
R/W
BWa
Control
logic
CLK
BWb
BWc
BWd
ADV / LD
LBO
1M x 32/36
SRAM
ZZ
CLK
Array
32/36
32/36
DQ[a,b,c,d]
Data
Input
Register
D
Q
32/36
32/36
CLK
32/36
CLK
CEN
Output
Buffer
OE
32/36
OE
DQ[a,b,c,d]
Selection guide
-75
8.5
7.5
325
140
90
-85
10
-10
12
Units
ns
Minimum cycle time
Maximum clock access time
Maximum operating current
Maximum standby current
8.5
300
130
90
10
ns
275
130
90
mA
mA
mA
Maximum CMOS standby current (DC)
12/23/04, v 1.1
Alliance Semiconductor
P. 1 of 18
Copyright © Alliance Semiconductor. All rights reserved.
ISSI [ INTEGRATED SILICON SOLUTION, INC ]
