AS7C33128PFD18B
February 2005
®
3.3V 128K × 18 pipeline burst synchronous SRAM
Features
• Multiple chip enables for easy expansion
• 3.3V core power supply
• Organization: 131,072 words × 18 bits
• Fast clock speeds to 200 MHz
• Fast clock to data access: 3.0/3.5/4.0 ns
• Fast OE access time: 3.0/3.5/4.0 ns
• Fully synchronous register-to-register operation
• Double-cycle deselect
• 2.5V or 3.3V I/O operation with separate V
• Linear or interleaved burst control
• Snooze mode for reduced power-standby
• Common data inputs and data outputs
DDQ
• Asynchronous output enable control
• Available in 100-pin TQFP package
• Individual byte write and global write
Logic block diagram
LBO
CLK
ADV
CLK
CS
CLR
Burst logic
128K × 18
Memory
array
ADSC
ADSP
17
Q
D
A[16:0]
Address
17
CS
15
17
register
CLK
18
18
GWE
D
Q
DQb
BW
b
Byte Write
registers
CLK
BWE
BW
D
Q
DQa
2
Byte Write
a
registers
CLK
CE0
CE1
OE
Output
registers
D
Q
Q
Input
registers
Enable
register
CE2
CE
CLK
CLK
CLK
D
Enable
delay
register
Power
down
ZZ
CLK
OE
18
DQ [a,b]
Selection guide
–200
5
–166
–133
7.5
133
4
Units
Minimum cycle time
6
ns
MHz
ns
Maximum clock frequency
Maximum clock access time
Maximum operating current
Maximum standby current
200
3.0
375
130
30
166
3.5
350
100
30
325
90
mA
mA
mA
Maximum CMOS standby current (DC)
30
1/31/05; v.1.2
Alliance Semiconductor
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