January 2005
AS7C331MFT18A
®
3.3V 1M x 18 Flow-through synchronous SRAM
Features
• Organization: 1,048,576 words x18 bits
• Fast clock to data access: 6.8/7.5/8.5/10 ns
• Fast OE access time: 3.5/4.0 ns
• Fully synchronous flow-through operation
• Asynchronous output enable control
• Available 100-pin TQFP packages
• Multiple chip enables for easy expansion
• 3.3 V core power supply
• 2.5 V or 3.3V I/O operation with separate VDDQ
• Linear or interleaved burst control
• Common data inputs and data outputs
• Snooze mode for reduced power-standby
•
Individual byte write and global write
Logic block diagram
LBO
CLK
ADV
ADSC
ADSP
CLK
CS
CLR
Burst logic
1M x 18
Memory
array
20 18
20
20
Q
D
A[19:0]
Address
CS
register
CLK
18
18
2
GWE
BWb
D
DQb
Byte Write
registers
CLK
Q
BWE
BWa
D
Q
DQa
Byte Write
registers
CLK
CE0
CE1
OE
Output
buffers
D
Q
Q
Input
registers
Enable
register
CE
CLK
CE2
CLK
D
Enable
delay
register
CLK
Power
down
ZZ
OE
18
DQ[a,b]
Selection guide
-68
7.5
6.8
285
90
-75
8.5
7.5
275
90
-85
10
-10
12
Units
ns
Minimum cycle time
Maximum clock access time
Maximum operating current
Maximum standby current
8.5
250
80
10
ns
230
80
mA
mA
mA
Maximum CMOS standby current (DC)
60
60
60
60
1/21/05, v 1.4
Alliance Semiconductor
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