December 2004
AS7C331MFT32A
AS7C331MFT36A
®
3.3V 1M × 32/36 Flow-through synchronous SRAM
Features
• Organization: 1,048,576 words × 32 or 36 bits
• Fast clock to data access: 7.5/8.5/10 ns
• Fast OE access time: 3.5/4.0 ns
• Fully synchronous flow-through operation
• Asynchronous output enable control
• Available in 100-pin TQFP package
• Individual byte write and global write
• Multiple chip enables for easy expansion
• 3.3V core power supply
• 2.5V or 3.3V I/O operation with separate V
• Linear or interleaved burst control
• Snooze mode for reduced power-standby
• Common data inputs and data outputs
DDQ
Logic block diagram
LBO
CLK
ADV
ADSC
ADSP
CLK
CE
Q0
Burst logic
CLR
1M × 32/36
Q1
Memory
array
2
2
D
CE
CLK
Q
A[19:0]
Address
20
20
18
20
register
32/36
32/36
GWE
BWE
BWd
D
Q
DQd
Byte write
registers
CLK
D
Q
DQc
Byte write
registers
BWc
BWb
CLK
D
Q
DQb
Byte write
registers
CLK
D
Q
DQa
Byte write
registers
4
BWa
CLK
CE0
CE1
OE
Output
registers
D
Q
Q
CE2
Input
registers
CLK
Enable
register
CE
CLK
CLK
D
Enable
Power
down
delay
register
CLK
ZZ
32/36
DQ[a:d]
OE
Selection guide
-75
8.5
7.5
325
140
90
-85
-10
12
Units
ns
Minimum cycle time
10
8.5
300
130
90
Maximum clock access time
Maximum operating current
Maximum standby current
10
ns
275
130
90
mA
mA
mA
Maximum CMOS standby current (DC)
12/23/04, v 1.3
Alliance Semiconductor
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