June 2002
Advance Information
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&
TM
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Features
• Organization: 1,048,576 words × 18 bits
• NTD architecture for efficient bus operation
• Available in 100-pin TQFP and 165-ball BGA package
• Byte write enables
™1
• Fast clock speeds to 250 MHz in LVTTL/ LVCMOS
• Fast clock to data access: 2.6/ 3/ 3.4/ 4 ns
• Fast OEaccess time: 2.6/ 3/ 3.4/ 4 ns
• Fully synchronous operation
• Clock enable for operation hold
• Multiple chip enables for easy expansion
• 3.3V core power supply
• 2.5V or 3.3V I/ O operation with separate V
DDQ
• “Flow-through” or “pipelined” mode
• Asynchronous output enable control
• Self-timed write cycles
• Interleaved or linear burst modes
• Snooze mode for standby operation
TM
1. NTD is a trademark of Alliance Semiconductor Corporation.
Logic block diagram
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Selection guide
-250
4
-200
5
-166
-100
10
Units
ns
Minimum cycle time
6
Maximum pipelined clock frequency
Maximum pipelined clock access time
Maximum operating current
250
2.6
400
160
30
200
3.0
400
160
30
166
3.4
350
120
30
100
4.0
230
70
MHz
ns
mA
mA
mA
Maximum standby current
Maximum CMOS standby current (DC)
30
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!ꢔꢉ"ꢉꢁ ꢉ"ꢜ
ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢉ'ꢉꢊꢋꢋꢅꢌꢍꢎꢏꢉꢐꢏꢑꢅꢎꢁꢍꢒꢓꢎꢈꢁꢄꢔꢉꢊꢋꢋꢉꢄꢅꢆꢇꢈꢕꢉꢄꢏꢕꢏꢄꢖꢏꢒꢔ
ISSI [ INTEGRATED SILICON SOLUTION, INC ]
