February 2005
AS7C331MPFD32A
AS7C331MPFD36A
®
3.3V 1M × 32/36 pipelined burst synchronous SRAM
Features
• Multiple chip enables for easy expansion
• 3.3V core power supply
• Organization: 1,048,576 words × 32 or 36 bits
• Fast clock speeds to 200 MHz
• 2.5V or 3.3V I/O operation with separate V
• Linear or interleaved burst control
• Snooze mode for reduced power-standby
• Common data inputs and data outputs
• Fast clock to data access: 3.1/3.5/3.8 ns
• Fast OE access time: 3.1/3.5/3.8 ns
• Fully synchronous register-to-register operation
• Double-cycle deselect
DDQ
• Asynchronous output enable control
• Available in 100-pin TQFP package
• Individual byte write and global write
Logic block diagram
LBO
CLK
ADV
ADSC
ADSP
CLK
CE
CLR
Q0
Burst logic
1M × 32/36
Q1
Memory
array
2
2
D
CE
CLK
Q
A[19:0]
Address
20
20
18
20
register
32/36
32/36
GWE
BWE
BWd
D
Q
DQd
Byte write
registers
CLK
D
Q
DQc
Byte write
registers
BWc
BWb
CLK
D
Q
DQb
Byte write
registers
CLK
D
Q
DQa
Byte write
registers
4
BWa
CLK
CE0
CE1
OE
Output
registers
D
Q
Q
CE2
Input
registers
CLK
Enable
register
CE
CLK
CLK
D
Enable
Power
down
delay
register
CLK
ZZ
32/36
DQ[a:d]
OE
Selection guide
-200
-166
-133
7.5
Units
ns
Minimum cycle time
5
6
Maximum clock frequency
Maximum clock access time
Maximum operating current
Maximum standby current
200
3.1
450
170
90
166
3.5
400
150
90
133
3.8
MHz
ns
350
140
90
mA
mA
mA
Maximum CMOS standby current (DC)
2/10/05, v.1.1
Alliance Semiconductor
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ISSI [ INTEGRATED SILICON SOLUTION, INC ]
