May 2003
Advance Information
AS7C331MPFS18A
®
1M x 18 pipelined burst synchronous SRAM
Features
• Organization: 1,048,576 x18 bits
• Available 100-pin TQFP and 165-ball BGA packages
• Byte write enables
• Multiple chip enables for easy expansion
• 3.3 V core power supply
• 2.5 V or 3.3V I/ O operation with separate VDDQ
• NTD™ pipelined architecture available (AS7C331MNTD18A,
AS7C33512NTD32A/ AS7C33512NTD36A)
• Fast clock speeds to 200MHz in LVTTL/ LVCMOS
• Fast clock to data access: 3/ 3.4/ 3.8 ns
• Fast OEaccess time: 3/ 3.4/ 3.8 ns
• Fully synchronous register-to-register operation
• Single register flow-through mode
• Single-cycle deselect
• Asynchronous output enable control
Logic block diagram
LBO
CLK
ADV
CLK
CS
CLR
ADSC
ADSP
Burst logic
20 18
1M ꢀ 18
Memory
array
20
20
AddresQs
register
D
A[19:0]
CS
CLK
18
18
2
GWE
D
Q
DQb
BW
b
Byte Write
registers
BWE
CLK
D
Q
DQa
BW
Byte Write
CLK
a
registers
CE0
CE1
CE2
OE
DEnableQ
register
Input
Output
registers
registers
CE
CLK
CLK
CLK
DEnableQ
Power
down
delay
ZZ
register
CLK
OE
18
DQ[a,b]
FT
Selection guide
-200
5
-166
-133
7.5
Units
ns
Minimum cycle time
6
Maximum clock frequency
200
3.0
370
130
70
166
3.4
340
120
70
133
3.8
MHz
ns
Maximum pipelined clock access time
Maximum operating current
Maximum standby current
320
110
70
mA
mA
mA
Maximum CMOS standby current (DC)
5/ 28/ 03, v. 052003 Advance Info
Alliance Semiconductor
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