May 2002
AS7C33256NTD32A
AS7C33256NTD36A
&
1
TM
ꢏꢐꢏꢑꢇꢒꢓꢔꢕꢖꢏꢒꢗꢏꢔꢇꢈꢘꢀꢙꢇꢚꢂꢍꢛꢇꢜꢝ
Features
• Organization: 262,144 words × 32 or 36 bits
• NTD architecture for efficient bus operation
• Available in 100-pin TQFP
• Byte write enables
™1
• Fast clock speeds to 166 MHz in LVTTL/ LVCMOS
• Fast clock to data access: 3.0/ 3.5/ 3.8/ 4/ 5 ns
• Fast OEaccess time: 3.5/ 3.8/ 4/ 5 ns
• Fully synchronous operation
• Clock enable for operation hold
• Multiple chip enables for easy expansion
• 3.3 core power supply
• 2.5V or 3.3V I/ O operation with separate V
DDQ
• “Flow-through” or “pipelined” mode
• Asynchronous output enable control
• 30 mW typical standby power
• Self-timed write cycles
• Interleaved or linear burst modes
• Snooze mode for standby operation
™
1. NTD is a trademark of Alliance Semiconductor Corporation.
Logic block diagram
18
18
Q
D Address
register
Burst logic
A[17:0]
CLK
D
Q
CE0
CE1
CE2
Write delay
addr. registers
CLK
18
R/W
BWa
BWb
BWc
Control
logic
CLK
BWd
256K x 32/ 36
SRAM
ADV / LD
FT
LBO
ZZ
CLK
Array
36/ 32
36/ 32
Data
Register
CLK
DATA [a:d]
Q
D Input
36/ 32
36/ 32
36/ 32
CLK
CEN
CLK
Output
Register
OE
36/ 32
DATA [a:d]
OE
Selection guide
-166
6
-150
6.7
-133
7.5
133
4
-100
10
Units
ns
Minimum cycle time
Maximum pipelined clock frequency
Maximum pipelined clock access time
Maximum operating current
166
3.0/ 3.51
150
3.8
100
5
MHz
ns
475
425
110
30
400
100
30
300
90
mA
mA
mA
Maximum standby current
130
Maximum CMOS standby current (DC)
30
30
1 3.0 ns available on 166 MHz parts with “H” suffix. For further information see page 7 and last page with ordering codes.
ꢉꢗꢘꢙꢘꢚꢛꢜꢉꢖꢔꢝꢔ ꢔꢛ!
ꢀꢁꢁꢂꢃꢄꢅꢆꢇꢈꢆꢉꢂꢅꢊꢄꢋꢌꢅꢍꢊꢎ
"ꢔꢉꢝꢉꢁ#ꢉꢝꢛ
ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢉ'ꢉꢊꢋꢋꢅꢌꢍꢎꢏꢉꢐꢏꢑꢅꢎꢁꢍꢒꢓꢎꢈꢁꢄꢔꢉꢊꢋꢋꢉꢄꢅꢆꢇꢈꢕꢉꢄꢏꢕꢏꢄꢖꢏꢒꢔ
ISSI [ INTEGRATED SILICON SOLUTION, INC ]
