December 2004
AS7C33256PFD32A
AS7C33256PFD36A
®
3.3V 256K × 32/36 pipelined burst synchronous SRAM
Features
• Organization: 262,144 words x 32 or 36 bits
• Fast clock speeds to 166 MHz
• Fast clock to data access: 3.5/4.0 ns
• Fast OE access time: 3.5/4.0 ns
• Fully synchronous register-to-register operation
• Dual-cycle deselect
• Individual byte write and global write
• Multiple chip enables for easy expansion
• Linear or interleaved burst control
• Snooze mode for reduced power-standby
• Common data inputs and data outputs
• 3.3V core power supply
• Asynchronous output enable control
• Available in100-pin TQFP
• 2.5V or 3.3V I/O operation with separate V
DDQ
Logic block diagram
LBO
CLK
CLK
CE
Q0
ADV
Burst logic
ADSC
CLR
256K × 32/36
Memory
array
Q1
18
ADSP
2
2
18
16
18
D
CE
CLK
Q
A
[17:0]
Address
register
36/32
36/32
BWE
GWE
d
D
Q
DQ
d
Byte write
BW
registers
CLK
D
Q
DQ
c
BW
c
Byte write
registers
CLK
D
Q
DQ
b
BW
b
Byte write
registers
CLK
D
Q
DQ
a
4
BW
a
Byte write
registers
CLK
D
CE0
CE1
CE2
OE
Q
Q
Output
Input
Enable
register
registers
registers
CE
CLK
CLK
CLK
D
Enable
Power
down
delay
ZZ
register
CLK
36/32
DQ[a:d]
OE
Selection guide
–166
6
–133
7.5
133
4
Units
Minimum cycle time
ns
MHz
ns
Maximum clock frequency
Maximum clock access time
Maximum operating current
Maximum standby current
166
3.5
475
130
30
425
100
30
mA
mA
mA
Maximum CMOS standby current (DC)
12/1/04, v.1.2
Alliance Semiconductor
P. 1 of 20
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ISSI [ INTEGRATED SILICON SOLUTION, INC ]
