April 2004
AS7C332MFT18A
®
3.3V 2M × 18 Flow-through synchronous SRAM
Features
• Organization: 2,097152 words × 18 bits
• Fast clock to data access: 6.5/7.5/8.5 ns
• Fast OE access time: 3.5/3.5/4.0 ns
• Fully synchronous flow-through operation
• Asynchronous output enable control
• Available in 100-pin TQFP package and 165-ball BGA
• Individual byte write and global write
• Multiple chip enables for easy expansion
• 3.3V core power supply
• Snooze mode for reduced power-standby
• Common data inputs and data outputs
• Boundary scan using IEEE 1149.1 JTAG function
1
• NTD™ pipelined architecture available
(AS7C332MNTD18A, AS7C331MNTD32A/
AS7C331MNTD36A)
1 NTD™ is a trademark of Alliance Semiconductor Corporation. All
trademarks mentioned in this document are the property of their
respective owners.
• 2.5V or 3.3V I/O operation with separate V
• Linear or interleaved burst control
DDQ
Logic block diagram
LBO
CLK
ADV
ADSC
ADSP
CLK
CS
Burst logic
2M x 18
CLR
Memory
array
21 19
21
21
Q
D
A[20:0]
Address
CS
register
CLK
18
18
2
GWE
BWb
D
DQb
Q
Byte Write
registers
BWE
BWa
CLK
D
Q
DQa
Byte Write
registers
CLK
CE0
CE1
OE
Output
D
Q
Q
Input
registers
Enable
register
CE
CLK
CE2
registers
CLK
CLK
D
Enable
delay
register
CLK
Power
down
ZZ
OE
18
DQ[a,b]
Selection guide
-65
7.5
-75
8.5
-85
10
Units
ns
Minimum cycle time
Maximum clock access time
Maximum operating current
Maximum standby current
Maximum CMOS standby current (DC)
6.5
7.5
8.5
270
130
110
ns
310
140
110
290
130
110
mA
mA
mA
4/26/04, v 1.0
Alliance Semiconductor
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