December 2004
AS7C332MNTD18A
®
3.3V 2M × 18 Pipelined SRAM with NTDTM
• Byte write enables
Features
• Clock enable for operation hold
• Multiple chip enables for easy expansion
• 3.3V core power supply
• Organization: 2,097,152 words × 18 bits
• NTD™ architecture for efficient bus operation
• Fast clock speeds to 200 MHz
• 2.5V or 3.3V I/O operation with separate VDDQ
• Self-timed write cycles
• Interleaved or linear burst modes
• Snooze mode for standby operation
• Fast clock to data access: 3.2/3.5/3.8 ns
• Fast OE access time: 3.2/3.5/3.8 ns
• Fully synchronous operation
• Common data inputs and data outputs
• Asynchronous output enable control
• Available in 100-pin TQFP package
Logic block diagram
21
21
Q
A[20:0]
D
Address
register
Burst logic
CLK
D
Q
CE0
CE1
CE2
Write delay
addr. registers
21
CLK
R/W
BWa
Control
logic
CLK
BWb
ADV / LD
LBO
2 M x 18
SRAM
Array
ZZ
CLK
18
18
DQ[a,b]
Data
Input
Register
D
Q
18
18
CLK
18
CLK
CEN
CLK
Output
Register
OE
18
OE
DQ[a,b]
Selection guide
-200
5
-166
6
-133
7.5
Units
ns
Minimum cycle time
Maximum clock frequency
Maximum clock access time
Maximum operating current
Maximum standby current
200
3.2
450
170
90
166
3.5
400
150
90
133
3.8
MHz
ns
350
140
90
mA
mA
mA
Maximum CMOS standby current (DC)
12/23/04, V 1.6
Alliance Semiconductor
P. 1 of 18
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