November 2004
AS7C33512FT18A
®
3.3V 512K × 18 Flow-through synchronous SRAM
Features
• Organization: 524,288 words × 18 bits
• Fast clock to data access: 7.5/8.5/10ns
• Fast OE access time: 3.5/4.0 ns
• Fully synchronous flow-through operation
• Asynchronous output enable control
• Available in 100-pin TQFP package
• Individual byte write and global write
• Multiple chip enables for easy expansion
• 3.3V core power supply
• 2.5V or 3.3V I/O operation with separate VDDQ
• Linear or interleaved burst control
• Snooze mode for reduced power-standby
• Common data inputs and data outputs
Logic block diagram
LBO
CLK
ADV
ADSC
ADSP
CLK
CS
Burst logic
512K x 18
CLR
Memory
array
19 17
19
19
Q
D
A[18:0]
Address
CS
register
CLK
18
18
2
GWE
BWb
D
DQb
Q
Byte Write
registers
BWE
BWa
CLK
D
Q
DQa
Byte Write
registers
CLK
CE0
CE1
OE
Output
D
Q
Q
Input
registers
Enable
register
CE
CLK
CE2
registers
CLK
CLK
D
Enable
delay
register
CLK
Power
down
ZZ
OE
18
DQ[a,b]
Selection guide
-75
8.5
7.5
300
110
30
-85
10
-10
12
Units
ns
Minimum cycle time
Maximum clock access time
Maximum operating current
Maximum standby current
Maximum CMOS standby current (DC)
8.5
275
100
30
10
ns
250
90
mA
mA
mA
30
11/30/04, v 1.1
Alliance Semiconductor
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