March 2002
AS7C33512NTD16A
AS7C33512NTD18A
®
TM
3.3V 512K × 16/18 ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢄꢉꢊꢋ
Features
• Available in100-pin TQFP and 119-ball BGA package
• Byte write enables
• Organization: 524,288 words × 16 or 18 bits
™
• NTD 1 architecture for efficient bus operation
• Multiple chip enables for easy expansion
• 3.3V core power supply
• 2.5V or 3.3V I/O operation with separate VDDQ
• 30 mW typical standby power in power down mode
• Self-timed WRITE cycles
• Fast clock speeds to 166 MHz in LVTTL/LVCMOS
• Fast clock to data access: 3.0/3.5/3.8/4.0/5.0 ns
• Fast OE access time: 3.5/3.8/4.0/5.0 ns
• Fully synchronous register-to-register operation
• “Flow-through” or “Pipeline” modes
• “Interleaved” or “Linear burst” modes
• Snooze mode for standby operation
• Asynchronous output enable control
™
1. NTD is a trademark of Alliance Semiconductor Corporation.
Logic block diagram
19
19
Q
D
A[18:0]
Address
register
Burst logic
CLK
D
Q
Write delay
addr. registers
CLK
CE0
CE1
CE2
19
R/W
BWa
BWb
Control
logic
CLK
ADV / LD
FT
512K x 16/18
SRAM
LBO
ZZ
Array
CLK
18/16
18/16
Data
DQ [a:b]
Q
D
Input
Register
18/16 18/16
CLK
18/16
CLK
CLK
CEN
Output
Register
OE
18/16
DQ[a:b]
OE
Selection Guide
-166
6
–150
6.6
–133
7.5
133
4
–100
10
Units
ns
Minimum cycle time
Maximum pipelined clock frequency
Maximum pipelined clock access time
Maximum operating current
166
3.0/3.51
150
3.8
100
5
MHz
ns
475
425
110
30
400
100
30
300
90
mA
mA
mA
Maximum standby current
130
Maximum CMOS standby current (DC)
30
30
1 3.0 ns available on 166 MHz parts with “H” suffix. For further information see page 7 and last page with ordering codes.
3/11/02; v.1.8H
Alliance Semiconductor
1 of 12
Copyright © Alliance Semiconductor. All rights reserved.
ISSI [ INTEGRATED SILICON SOLUTION, INC ]
