AS7C33512NTF18A
July 2004
®
3.3V 512K×18 Flowthrough Synchronous SRAM with NTDTM
Features
• Organization: 524,288 words × 18 bits
• NTD™1 architecture for efficient bus operation
• Fast clock to data access: 6.5/7.5 ns
• Fast OE access time: 3.5 ns
• Available in 100-pin TQFP
• Byte write enables
• Clock enable for operation hold
• Multiple chip enables for easy expansion
• 3.3 core power supply
• Fully synchronous operation
• Flow-through mode
• Asynchronous output enable control
• 2.5V or 3.3V I/O operation with separate VDDQ
• 30 mW typical standby power
• Self-timed write cycles
• Interleaved or linear burst modes
• Snooze mode for standby operation
1. NTD is a trademark of Alliance Semiconductor Corporation. All
trademarks mentioned in this document are the property of their respective
owners.
Logic Block Diagram
19
19
A[18:0]
Q
D
Address
register
burst logic
CLK
D
Q
CE0
CE1
CE2
Write delay
addr. registers
CLK
19
R/W
BWa
BWb
Control
logic
CLK
ADV / LD
FT
512K x 18
SRAM
array
LBO
ZZ
CLK
18
18
DQ [a,b]
Data
input
register
D
Q
18
18
CLK
18
CLK
CEN
Output
buffer
OE
18
OE
DQ [a,b]
Selection Guide
–65
7.5
6.5
250
120
30
-75
8.5
7.5
225
100
30
Units
ns
Minimum cycle time
Maximum clock access time
Maximum operating current
Maximum standby current
ns
mA
mA
mA
Maximum CMOS standby current (DC)
7/12/04, v. 1.0
Alliance Semiconductor
P. 1 of 14
Copyright © Alliance Semiconductor. All rights reserved.
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